Re: [PATCH] RTL: Bugfix for wrong code with v16hi compare & mask

[Jeff Law via Gcc-patches]

On 3/26/23 19:36, Hongtao Liu wrote:

On Sun, Mar 26, 2023 at 3:01 AM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:

On 3/24/23 08:11, pan2.li--- via Gcc-patches wrote:

From: Pan Li <pan2...@intel.com>

Fix the bug of the incorrect code generation for the
below code sample.

typedef unsigned short __attribute__((__vector_size__ (32))) V;
typedef unsigned short u16;

void
foo (V m, u16 *ret)
{
    V v = 6 > ((V) { 2049, 8 } & m);
    *ret = v[0]; // + a + b + c + d;
}

Before this patch.
addi    sp,sp,-64
ld      a5,0(a0)
li      a4,528384
addi    a4,a4,-2047
and     a5,a5,a4
// slli    a5,a5,48 <- eliminated by mistake
// srli    a5,a5,48 <- eliminated by mistake
sltiu   a5,a5,6
negw    a5,a5
sh      a5,0(a1)

After this patch.
addi    sp,sp,-64
ld      a5,0(a0)
li      a4,528384
addi    a4,a4,-2047
and     a5,a5,a4
slli    a5,a5,48
srli    a5,a5,48
sltiu   a5,a5,6
negw    a5,a5
sh      a5,0(a1)

The simplify_comparation for the AND operation will
try to simplify below RTL code from:
(and:DI (subreg:DI (reg:HI 154) 0) (const_int 0x801))
to:
(subreg:DI (and (reg:HI 154) (const_int 0x801)) 0)

These look equivalent to me -- assuming they're used as rvalues.

They're equivalent only when WORD_REGISTER_OPERATIONS, orelse the
upper bits of latter is UD, but the former is 0.

Yea my bad.  I need to look at this again.
jeff