On 3/5/23 12:03, Andrew Pinski wrote:
On Sun, Mar 5, 2023 at 10:14 AM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
On 2/23/23 14:23, Andrew Pinski via Gcc-patches wrote:
On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly
<rzin...@ventanamicro.com> wrote:
Changes since v1:
- Fixed formatting issues.
- Added a name to the define_insn_and_split pattern.
- Set the target on the 'dg-do compile' in pr106602.c.
- Removed the rv32 restriction in pr95632.c.
-- >8 --
Due to RISC-V limitations on operations with big constants combine
is failing to match such operations and is not being able to
produce optimal code as it keeps splitting them. By pretending we
can do those operations we can get more opportunities for
simplification of surrounding instructions.
2022-12-06 Raphael Moreira Zinsly <rzin...@ventanamicro.com>
Jeff Law <j...@ventanamicro.com>
gcc/Changelog:
PR target/95632
PR target/106602
* config/riscv/riscv.md: New pattern to simulate complex
const_int loads.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr95632.c: New test.
* gcc.target/riscv/pr106602.c: New test.
---
gcc/config/riscv/riscv.md | 15 +++++++++++++++
gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++
gcc/testsuite/gcc.target/riscv/pr95632.c | 15 +++++++++++++++
3 files changed, 44 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c
create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index df57e2b0b4a..b0daa4b19eb 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1667,6 +1667,21 @@
MAX_MACHINE_MODE, &operands[3], TRUE);
})
+;; Pretend to have the ability to load complex const_int in order to get
+;; better code generation around them.
+(define_insn_and_split "*mvconst_internal"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
+ "cse_not_expected"
This is just way broken. This should be combined with the normal move
instructions and just be a define_split.
See PR 108892 for a testcase which shows this breaking how the
register allocator thinks it should work.
I'm pretty sure that won't work. You need them exposed as a define_insn
so that they can act as a bridge pattern for combine. You don't want to
expose before combine as that'll regress things in a variety of other
ways. You don't want the bridge form to survive after splitting. Hence
define_insn_and_split.
I haven't looked at that bug in detail, but Raphael and I certainly will.
So the register allocator does not know how to handle if there are two
different patterns which are to be used but differ by
constraints/predicats. This is especially true for mov instructions
which this is.
The define_insn_and_split for this case shouldn't be available for the
allocator. If it is, then that's the source of the problem. We may
have missed something in the predicates.
What I am saying is the "*movdi_64bit" and "*movsi_internal" patterns
should handle the same instruction as the above and still have a
define_split.
Perhaps but I think that's independent of the problem you're bumping up
against. Also note that by the time we're in the allocator we have to
be more careful as we can't allocate new pseudos.
Take a look at how aarch64 handles this here. It has one pattern for
the move but it is a define_insn_and_split still. This is explicitly
to handle the case you are doing really.
"*movsi_aarch64" and "*movdi_aarch64" .
Will do.
Jeff
