Re: [PATCH v4 5/9] riscv: thead: Add support for the XTheadBb ISA extension

[Jeff Law via Gcc-patches]

On 3/2/23 01:35, Christoph Muellner wrote:
From: Christoph Müllner <christoph.muell...@vrull.eu>

This patch adds support for the XTheadBb ISA extension.
Thus, there is a functional overlap of the new instructions with
existing Bitmanip instruction, which allows a good amount of code
sharing. However, the vendor extensions are cleanly separated from
the standard extensions (e.g. by using INSN expand pattern that
will re-emit RTL that matches the patterns of either Bitmanip or
XThead INSNs).


diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d6c2265e9d4..fc8ce9f5226 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3087,6 +3087,26 @@ (define_insn "riscv_prefetchi_<mode>"
    "prefetch.i\t%a0"
  )
  
+(define_expand "extv<mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+       (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
+                        (match_operand 2 "const_int_operand")
+                        (match_operand 3 "const_int_operand")))]
+  "TARGET_XTHEADBB"
+)
+
+(define_expand "extzv<mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+       (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
+                        (match_operand 2 "const_int_operand")
+                        (match_operand 3 "const_int_operand")))]
+  "TARGET_XTHEADBB"
+{
+  if (TARGET_XTHEADBB
+      && (INTVAL (operands[2]) < 8) && (INTVAL (operands[3]) == 0))
+    FAIL;
+})
Note that bitmanip has single bit extractions which probably should be 
handed by extzv rather than relying strictly on the combiner to 
synthesize them.  Similarly for single bit insertions.

I've actually got a TODO on Raphael's plate to see how renaming the 
existing bitmanip bit extraction to extzv affects code generation.  I'm 
not offhand sure where it is on his priority list yet.

I guess the wider point is the ext and ins expanders should probably be 
accepting single bit extractions/insertions when ZBS is enabled.

Jeff