From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
To be consistent with other naming of preds array variable.
Change tu_preds into none_tu_preds which indicate such preds
include vop and vop_tu combinations.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (vadc): Rename.
(vsbc): Ditto.
(vmerge): Ditto.
(vmv_v): Ditto.
* config/riscv/riscv-vector-builtins.cc: Ditto.
---
.../riscv/riscv-vector-builtins-functions.def | 16 ++++++++--------
gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 9bad1373bfd..e6c19691d17 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -113,14 +113,14 @@ DEF_RVV_FUNCTION (vsext, alu, full_preds, i_vf4_ops)
DEF_RVV_FUNCTION (vsext, alu, full_preds, i_vf8_ops)
// 11.4. Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
-DEF_RVV_FUNCTION (vadc, no_mask_policy, tu_preds, iu_vvvm_ops)
-DEF_RVV_FUNCTION (vadc, no_mask_policy, tu_preds, iu_vvxm_ops)
+DEF_RVV_FUNCTION (vadc, no_mask_policy, none_tu_preds, iu_vvvm_ops)
+DEF_RVV_FUNCTION (vadc, no_mask_policy, none_tu_preds, iu_vvxm_ops)
DEF_RVV_FUNCTION (vmadc, return_mask, none_preds, iu_mvvm_ops)
DEF_RVV_FUNCTION (vmadc, return_mask, none_preds, iu_mvxm_ops)
DEF_RVV_FUNCTION (vmadc, return_mask, none_preds, iu_mvv_ops)
DEF_RVV_FUNCTION (vmadc, return_mask, none_preds, iu_mvx_ops)
-DEF_RVV_FUNCTION (vsbc, no_mask_policy, tu_preds, iu_vvvm_ops)
-DEF_RVV_FUNCTION (vsbc, no_mask_policy, tu_preds, iu_vvxm_ops)
+DEF_RVV_FUNCTION (vsbc, no_mask_policy, none_tu_preds, iu_vvvm_ops)
+DEF_RVV_FUNCTION (vsbc, no_mask_policy, none_tu_preds, iu_vvxm_ops)
DEF_RVV_FUNCTION (vmsbc, return_mask, none_preds, iu_mvvm_ops)
DEF_RVV_FUNCTION (vmsbc, return_mask, none_preds, iu_mvxm_ops)
DEF_RVV_FUNCTION (vmsbc, return_mask, none_preds, iu_mvv_ops)
@@ -230,12 +230,12 @@ DEF_RVV_FUNCTION (vwmaccsu, alu, full_preds,
i_su_wwxv_ops)
DEF_RVV_FUNCTION (vwmaccus, alu, full_preds, i_us_wwxv_ops)
// 11.15. Vector Integer Merge Instructions
-DEF_RVV_FUNCTION (vmerge, no_mask_policy, tu_preds, all_vvvm_ops)
-DEF_RVV_FUNCTION (vmerge, no_mask_policy, tu_preds, iu_vvxm_ops)
+DEF_RVV_FUNCTION (vmerge, no_mask_policy, none_tu_preds, all_vvvm_ops)
+DEF_RVV_FUNCTION (vmerge, no_mask_policy, none_tu_preds, iu_vvxm_ops)
// 11.16 Vector Integer Move Instructions
-DEF_RVV_FUNCTION (vmv_v, move, tu_preds, all_v_ops)
-DEF_RVV_FUNCTION (vmv_v, move, tu_preds, iu_x_ops)
+DEF_RVV_FUNCTION (vmv_v, move, none_tu_preds, all_v_ops)
+DEF_RVV_FUNCTION (vmv_v, move, none_tu_preds, iu_x_ops)
/* 12. Vector Fixed-Point Arithmetic Instructions. */
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 54681bab3ea..97ca1f11541 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -481,7 +481,7 @@ static CONSTEXPR const predication_type_index full_preds[]
PRED_TYPE_tumu, PRED_TYPE_mu, NUM_PRED_TYPES};
/* vop/vop_tu will be registered. */
-static CONSTEXPR const predication_type_index tu_preds[]
+static CONSTEXPR const predication_type_index none_tu_preds[]
= {PRED_TYPE_none, PRED_TYPE_tu, NUM_PRED_TYPES};
/* vop/vop_m will be registered. */
--
2.36.3
