[PATCH] RISC-V: Add vmsge vv C++ tests

juzhe . zhong Mon, 13 Feb 2023 00:38:01 -0800

From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>

gcc/testsuite/ChangeLog:


        * g++.target/riscv/rvv/base/vmsge_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv_m-1.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv_m-2.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv_m-3.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vmsge_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C: New test.
---
 .../g++.target/riscv/rvv/base/vmsge_vv-1.C    | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv-2.C    | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv-3.C    | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv_m-1.C  | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv_m-2.C  | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv_m-3.C  | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv_mu-1.C | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv_mu-2.C | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsge_vv_mu-3.C | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsgeu_vv-1.C   | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsgeu_vv-2.C   | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsgeu_vv-3.C   | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C | 160 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgeu_vv_mu-1.C           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgeu_vv_mu-2.C           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsgeu_vv_mu-3.C           | 160 ++++++++++++++++++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-1.C
new file mode 100644
index 00000000000..556a900decc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsge(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-2.C
new file mode 100644
index 00000000000..f86b97d4571
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsge(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-3.C
new file mode 100644
index 00000000000..f20b69be8eb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsge(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-1.C
new file mode 100644
index 00000000000..2c24950d1bf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsge(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-2.C
new file mode 100644
index 00000000000..fb2b3e91751
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsge(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-3.C
new file mode 100644
index 00000000000..a42b1b80b34
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsge(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsge(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t 
vl)
+{
+    return __riscv_vmsge(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-1.C
new file mode 100644
index 00000000000..770ebad62e1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsge_mu(vbool2_t mask,vbool2_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsge_mu(vbool1_t mask,vbool1_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsge_mu(vbool2_t mask,vbool2_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-2.C
new file mode 100644
index 00000000000..d8134cf0ded
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsge_mu(vbool2_t mask,vbool2_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsge_mu(vbool1_t mask,vbool1_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsge_mu(vbool2_t mask,vbool2_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-3.C
new file mode 100644
index 00000000000..496acb9aeb2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsge_mu(vbool2_t mask,vbool2_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsge_mu(vbool1_t mask,vbool1_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsge_mu(vbool2_t mask,vbool2_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsge_mu(vbool4_t mask,vbool4_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsge_mu(vbool64_t mask,vbool64_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsge_mu(vbool32_t mask,vbool32_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsge_mu(vbool16_t mask,vbool16_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsge_mu(vbool8_t mask,vbool8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsge_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-1.C
new file mode 100644
index 00000000000..01f996d2d7b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgeu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-2.C
new file mode 100644
index 00000000000..58988b9a480
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgeu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-3.C
new file mode 100644
index 00000000000..7dbac011111
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgeu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C
new file mode 100644
index 00000000000..5edf660242b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgeu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C
new file mode 100644
index 00000000000..ea67833bbb3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgeu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C
new file mode 100644
index 00000000000..c8cb3d8bcf3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgeu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgeu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vmsgeu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C
new file mode 100644
index 00000000000..d1594636af9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t 
op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t 
op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t 
op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t 
op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t 
op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgeu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t 
op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsgeu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t 
op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t 
op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t 
op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t 
op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t 
op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t 
op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsgeu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t 
op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t 
op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t 
op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t 
op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t 
op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t 
op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t 
op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t 
op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t 
op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t 
op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C
new file mode 100644
index 00000000000..ff8ed6dc4e8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t 
op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t 
op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t 
op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t 
op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t 
op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgeu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t 
op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsgeu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t 
op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t 
op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t 
op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t 
op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t 
op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t 
op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsgeu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t 
op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t 
op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t 
op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t 
op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t 
op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t 
op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t 
op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t 
op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t 
op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t 
op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C
new file mode 100644
index 00000000000..0630c3f4c81
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t 
op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t 
op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t 
op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t 
op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t 
op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgeu_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t 
op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsgeu_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t 
op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t 
op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t 
op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t 
op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t 
op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t 
op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsgeu_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t 
op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t 
op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t 
op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t 
op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t 
op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsgeu_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t 
op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsgeu_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t 
op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsgeu_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t 
op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsgeu_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t 
op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsgeu_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t 
op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsgeu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
-- 
2.36.3

[PATCH] RISC-V: Add vmsge vv C++ tests

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