Hi Haochen, Thanks for the explanation.
on 2022/11/21 14:18, HAO CHEN GUI wrote: > Hi Segher, > > 在 2022/11/18 20:18, Segher Boessenkool 写道: >> I don't think we should pretend we have any conditional jumps the >> machine does not actually have, in cbranchcc4. When would this ever be >> useful? cror;beq can be quite expensive, compared to the code it would >> replace anyway. >> >> If something generates those here (which then ICEs later), that is >> wrong, fix *that*? Is it ifcvt doing it? > > "*cbranch_2insn" is a valid insn for rs6000. So it generates such insn > at expand pass. The "prepare_cmp_insn" called by ifcvt just wants to verify > that the following comparison rtx is valid. Maybe we can adjust prepare_cmp_insn to fail if the constructed cbranchcc4 pattern doesn't satisfy the predicate of operand 0 rather than to assert. It's something like: if (!insn_operand_matches (icode, 0, test)) goto fail; or only assign and return if insn_operand_matches (icode, 0, test). The code makes the assumption that all this kind of cbranchcc4 patterns should match what target defines for cbranchcc4 optab, but unfortunately it's not sure for our port and I don't see how it should be. BR, Kewen
