> + {"zihpm", ISA_SPEC_CLASS_NONE, 0, 1},
See above.
> +
> {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
There's some missing ones, just poking through the profile I can find:
Za64rs and Zic64b, but there's a lot in there and I'm kind of getting my
eyes crossed already.
I'd argue that Za64rs should be handled like Ziccif, but we don't have a
lot of bits left in the header. I just sent some patches to the ELF
psABI spec: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/351
> @@ -219,6 +228,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
>
> {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
> {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"svpbmt", ISA_SPEC_CLASS_NONE, 0, 1},
>
> /* Terminate the list. */
> {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> @@ -1179,6 +1189,14 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
>
> {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
> {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
> + {"ziccamoa", &gcc_options::x_riscv_zi_subext, MASK_ZICCAMOA},
> + {"ziccif", &gcc_options::x_riscv_zi_subext, MASK_ZICCIF},
> + {"zicclsm", &gcc_options::x_riscv_zi_subext, MASK_ZICCLSM},
> + {"ziccrse", &gcc_options::x_riscv_zi_subext, MASK_ZICCRSE},
> + {"zicntr", &gcc_options::x_riscv_zi_subext, MASK_ZICNTR},
> +
> + {"zihintpause", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
> + {"zihpm", &gcc_options::x_riscv_zi_subext, MASK_ZIHPM},
>
> {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
> {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
> @@ -1230,6 +1248,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
> {"zvl1024b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL1024B},
> {"zvl2048b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL2048B},
> {"zvl4096b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL4096B},
> +
Looks like a spurious newline got inserted? If there's a reason for it
then it's best to do this as its own commit.
> {"zvl8192b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL8192B},
> {"zvl16384b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL16384B},
> {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
> @@ -1242,6 +1261,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
>
> {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
> {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
> + {"svpbmt", &gcc_options::x_riscv_sv_subext, MASK_SVPBMT},
Not technically part of the profiles so we could split it out, but I
don't think it's strictly necessary.
> {NULL, NULL, 0}
> };
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 1dfe8c89209..906b6280188 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -69,9 +69,23 @@ enum stack_protector_guard {
>
> #define MASK_ZICSR (1 << 0)
> #define MASK_ZIFENCEI (1 << 1)
> +#define MASK_ZICCAMOA (1 << 2)
> +#define MASK_ZICCIF (1 << 3)
> +#define MASK_ZICCLSM (1 << 4)
> +#define MASK_ZICCRSE (1 << 5)
> +#define MASK_ZICNTR (1 << 6)
> +#define MASK_ZIHINTPAUSE (1 << 7)
> +#define MASK_ZIHPM (1 << 8)
>
> #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
> #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
> +#define TARGET_ZICCAMOA ((riscv_zi_subext & MASK_ZICCAMOA) != 0)
> +#define TARGET_ZICCIF ((riscv_zi_subext & MASK_ZICCIF) != 0)
> +#define TARGET_ZICCLSM ((riscv_zi_subext & MASK_ZICCLSM) != 0)
> +#define TARGET_ZICCRSE ((riscv_zi_subext & MASK_ZICCRSE) != 0)
> +#define TARGET_ZICNTR ((riscv_zi_subext & MASK_ZICNTR) != 0)
> +#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
> +#define TARGET_ZIHPM ((riscv_zi_subext & MASK_ZIHPM) != 0)
>
> #define MASK_ZBA (1 << 0)
> #define MASK_ZBB (1 << 1)
> @@ -174,6 +188,7 @@ enum stack_protector_guard {
>
> #define MASK_SVINVAL (1 << 0)
> #define MASK_SVNAPOT (1 << 1)
> +#define MASK_SVPBMT (1 << 2)
>
> #define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
> #define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
