Re: [PATCH v2] RISC-V: Libitm add RISC-V support.

[Jeff Law via Gcc-patches]

On 10/27/22 06:49, Xiongchuan Tan via Gcc-patches wrote:
libitm/ChangeLog:

         * configure.tgt: Add riscv support.
         * config/riscv/asm.h: New file.
         * config/riscv/sjlj.S: New file.
         * config/riscv/target.h: New file.
---
v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

  libitm/config/riscv/asm.h    |  52 +++++++++++++
  libitm/config/riscv/sjlj.S   | 144 +++++++++++++++++++++++++++++++++++
  libitm/config/riscv/target.h |  50 ++++++++++++
  libitm/configure.tgt         |   2 +
  4 files changed, 248 insertions(+)
  create mode 100644 libitm/config/riscv/asm.h
  create mode 100644 libitm/config/riscv/sjlj.S
  create mode 100644 libitm/config/riscv/target.h

Not objecting or even reviewing....  But hasn't transactional memory 
largely fallen out of favor these days?  Intel has pulled it and I think 
IBM did as well.    Should we be investing in extending libitm at all?


jeff