Thanks, committed!
On Tue, Aug 30, 2022 at 2:15 PM <juzhe.zh...@rivai.ai> wrote:
>
> From: zhongjuzhe <juzhe.zh...@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add
> "vr" constraint.
> (TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint.
> (TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint.
> (vp): Add poly constraint.
>
> ---
> gcc/config/riscv/constraints.md | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2873d533cb5..669e5ed734b 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -108,3 +108,23 @@
> A constant @code{move_operand}."
> (and (match_operand 0 "move_operand")
> (match_test "CONSTANT_P (op)")))
> +
> +;; Vector constraints.
> +
> +(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
> + "A vector register (if available).")
> +
> +(define_register_constraint "vd" "TARGET_VECTOR ? VD_REGS : NO_REGS"
> + "A vector register except mask register (if available).")
> +
> +(define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS"
> + "A vector mask register (if available).")
> +
> +;; This constraint is used to match instruction "csrr %0, vlenb" which is
> generated in "mov<mode>".
> +;; VLENB is a run-time constant which represent the vector register length
> in bytes.
> +;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register
> length in bytes.
> +;; We should only allow the poly equal to BYTES_PER_RISCV_VECTOR.
> +(define_constraint "vp"
> + "POLY_INT"
> + (and (match_code "const_poly_int")
> + (match_test "known_eq (rtx_to_poly_int64 (op),
> BYTES_PER_RISCV_VECTOR)")))
> \ No newline at end of file
> --
> 2.36.1
>
