Prathamesh Kulkarni <prathamesh.kulka...@linaro.org> writes: > Hi Richard, > Following from off-list discussion, in the attached patch, I wrote pattern > similar to vec_duplicate<mode>_reg, which seems to work for the svld1rq tests. > Does it look OK ? > > Sorry, I didn't fully understand your suggestion on integrating with > vec_duplicate<mode>_reg > pattern. For vec_duplicate<mode>_reg, the operand to vec_duplicate expects > mode to be <VEL>, while the pattern in patch expects operand of > vec_duplicate to have mode <V128>. > How do we write a pattern so an operand can accept either of the 2 modes ?
I quoted the wrong one, sorry, should have been aarch64_vec_duplicate_vq<mode>_le. > Also it seems <V128> cannot be used with SVE_ALL ? Yeah, these would be SVE_FULL only. Richard
