On Sat, Mar 26, 2022 at 1:27 AM H.J. Lu via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Since PHADDW/PHADDD/PHADDSW/PHSUBW/PHSUBD/PHSUBSW/PSIGNB/PSIGNW/PSIGND > have no AVX512 version, replace the "Yv" register constraint with the > "x" register constraint. LGTM, please backport to GCC10/GCC11 branch. > > PR target/105052 > * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3): > Replace "Yv" with "x". > (ssse3_ph<plusminus_mnemonic>dv2si3): Likewise. > (ssse3_psign<mode>3): Likewise. > --- > gcc/config/i386/sse.md | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 6f7af2f21d6..aae29cd462f 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -20112,12 +20112,12 @@ (define_insn "ssse3_ph<plusminus_mnemonic>wv8hi3" > (set_attr "mode" "TI")]) > > (define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3" > - [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") > + [(set (match_operand:V4HI 0 "register_operand" "=y,x,x") > (ssse3_plusminus:V4HI > (vec_select:V4HI > (vec_concat:V8HI > - (match_operand:V4HI 1 "register_operand" "0,0,Yv") > - (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")) > + (match_operand:V4HI 1 "register_operand" "0,0,x") > + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,x")) > (parallel > [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])) > (vec_select:V4HI > @@ -20199,12 +20199,12 @@ (define_insn "ssse3_ph<plusminus_mnemonic>dv4si3" > (set_attr "mode" "TI")]) > > (define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3" > - [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") > + [(set (match_operand:V2SI 0 "register_operand" "=y,x,x") > (plusminus:V2SI > (vec_select:V2SI > (vec_concat:V4SI > - (match_operand:V2SI 1 "register_operand" "0,0,Yv") > - (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")) > + (match_operand:V2SI 1 "register_operand" "0,0,x") > + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,x")) > (parallel [(const_int 0) (const_int 2)])) > (vec_select:V2SI > (vec_concat:V4SI (match_dup 1) (match_dup 2)) > @@ -20702,10 +20702,10 @@ (define_insn "<ssse3_avx2>_psign<mode>3" > (set_attr "mode" "<sseinsnmode>")]) > > (define_insn "ssse3_psign<mode>3" > - [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") > + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x") > (unspec:MMXMODEI > - [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv") > - (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")] > + [(match_operand:MMXMODEI 1 "register_operand" "0,0,x") > + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")] > UNSPEC_PSIGN))] > "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" > "@ > -- > 2.35.1 >
-- BR, Hongtao
