Hi,
This patch updates the register move tunings for
-mcpu/-mtune={neoverse-v1,neoverse-512tvb}.
2022-03-16 Tamar Christina <tamar.christ...@arm.com>
Andre Vieira <andre.simoesdiasvie...@arm.com>
* config/aarch64/aarch64.cc (neoversev1_regmove_cost): New
tuning struct.
(neoversev1_tunings): Use neoversev1_regmove_cost and update
store_int cost.
(neoverse512tvb_tunings): Likewise.
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index
9b6f67dc592d8a447d6b28390c90abe5dcfa5f08..f0485574528c47221e17a3aa5aee70a56508f61e
100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -670,6 +670,16 @@ static const struct cpu_regmove_cost
neoversen2_regmove_cost =
2 /* FP2FP */
};
+static const struct cpu_regmove_cost neoversev1_regmove_cost =
+{
+ 1, /* GP2GP */
+ /* Spilling to int<->fp instead of memory is recommended so set
+ realistic costs compared to memmv_cost. */
+ 3, /* GP2FP */
+ 2, /* FP2GP */
+ 2 /* FP2FP */
+};
+
static const struct cpu_regmove_cost demeter_regmove_cost =
{
1, /* GP2GP */
@@ -2063,13 +2073,13 @@ static const struct tune_params neoversev1_tunings =
{
&cortexa76_extra_costs,
&neoversev1_addrcost_table,
- &generic_regmove_cost,
+ &neoversev1_regmove_cost,
&neoversev1_vector_cost,
&generic_branch_cost,
&generic_approx_modes,
SVE_256, /* sve_width */
{ 4, /* load_int. */
- 1, /* store_int. */
+ 2, /* store_int. */
6, /* load_fp. */
2, /* store_fp. */
6, /* load_pred. */
@@ -2200,13 +2210,13 @@ static const struct tune_params neoverse512tvb_tunings =
{
&cortexa76_extra_costs,
&neoversev1_addrcost_table,
- &generic_regmove_cost,
+ &neoversev1_regmove_cost,
&neoverse512tvb_vector_cost,
&generic_branch_cost,
&generic_approx_modes,
SVE_128 | SVE_256, /* sve_width */
{ 4, /* load_int. */
- 1, /* store_int. */
+ 2, /* store_int. */
6, /* load_fp. */
2, /* store_fp. */
6, /* load_pred. */
