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At 2012-02-03 10:09:55,"Xinyu Qi" <x...@marvell.com> wrote: > PING > > http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01786.html > > At 2011-12-29 14:12:44,"Xinyu Qi" <x...@marvell.com> wrote: > > At 2011-12-22 17:53:45,"Richard Earnshaw" <rearn...@arm.com> wrote: > > > On 22/12/11 06:38, Xinyu Qi wrote: > > > > At 2011-12-15 01:32:13,"Richard Earnshaw" <rearn...@arm.com> > wrote: > > > >> On 24/11/11 01:33, Xinyu Qi wrote: > > > >>> Hi Ramana, > > > >>> > > > >>> I solve the conflict, please try again. The new diff is attached. > > > >>> > > > >>> Thanks, > > > >>> Xinyu > > > >>> > > > >>> At 2011-11-19 07:36:15,"Ramana Radhakrishnan" > > > >> <ramana.radhakrish...@linaro.org> wrote: > > > >>>> > > > >>>> Hi Xinyu, > > > >>>> > > > >>>> This doesn't apply cleanly currently on trunk and the reject > > > >>>> appears to come from iwmmxt.md and I've not yet investigated why. > > > >>>> > > > >>>> Can you have a look ? > > > >>>> > > > >> > > > >> This patch is NOT ok. > > > >> > > > >> You're adding features that were new in iWMMXt2 (ie not in the > > > >> original > > > >> implementation) but you've provided no means by which the compiler > > > >> can detect which operations are only available on the new cores. > > > > > > > > Hi Richard, > > > > > > > > All of the WMMX chips support WMMX2 instructions. > > > > > > This may be true for Marvell's current range of processors, but I find > > > it hard to reconcile with the assembler support in GAS, which clearly > > > distinguishes between iWMMXT and iWMMXT2 instruction sets. Are you > > > telling me that no cores were ever manufactured (even by Intel) that > > > only supported iWMMXT? > > > > > > I'm concerned that this patch will break support for existing users > > > who have older chips (for GCC we have to go through a deprecation > > > cycle if we want to drop support for something we now believe is > > > no-longer worth maintaining). > > > > > > > What I do is to complement the WMMX2 intrinsic support in GCC. > > > > > > I understand that, and I'm not saying the patch can never go in; just > > > that it needs to separate out the support for the different > > > architecture variants. > > > > > > > I don't think it is necessary for users to consider whether one WMMX > > > > insn is a > > > WMMX2 insn or not. > > > > > > Users don't (unless they want their code to run on legacy processors > > > that only support the original instruction set), but the compiler > > > surely must know what it is targeting. Remember that the instruction > > > patterns are not entirely black boxes, the compiler can do > > > optimizations on intrinsics (it's one of the reasons why they are > > > better than inline assembly). Unless the compiler knows exactly what > > > instructions are legal, it could end up optimizing something that > > > started as a WMMX insn into something that's a WMMX2 insn (for > > > example, propagating a constant into a vector shift expression). > > > > > > R. > > > > Hi, Richard, > > > > You are right. There exist the chips that only support WMMX instructions in > the > > history. > > I distinguish the iWMMXt and iWMMXt2 in the patch update this time. > > > > In current GCC, -march=iwmmxt and -march=iwmmxt2 (or -mcpu=iwmmxt > and > > -mcpu=iwmmxt2) are almost no difference in the compiling stage. > > I take advantage of them to do the work, that is, make -march=iwmmxt (or > > -mcpu=iwmmxt) only support iWMMXt intrinsic iWMMXt built in and WMMX > > instructions, and make -march=iwmmxt2 (or -mcpu=iwmmxt2) support fully > > iWMMXt2. > > > > Define a new flag FL_IWMMXT2 to represent the chip support iWMMXt2 > > extension, which directly controls the iWMMXt2 built in initialization and > > the > > followed defines. > > Define __IWMMXT2__ in TARGET_CPU_CPP_BUILTINS to control the access > of > > iWMMXt2 intrinsics. > > Define TARGET_REALLY_IWMMXT2 to control the access of WMMX2 > > instructions' machine description. > > In arm.md, define iwmmxt2 in "arch" attr to control the access of the > > alternative in shift patterns. > > > > The updated patch 4/5 is attached here. 1/5, 2/5 and 3/5 are updated > > accordingly. Attach them in related mails. > > Please take a look if such modification is proper. > > > > Changelog: > > > > * config/arm/arm.c (arm_output_iwmmxt_shift_immediate): New > > function. > > (arm_output_iwmmxt_tinsr): Likewise. > > * config/arm/arm-protos.h (arm_output_iwmmxt_shift_immediate): > > Declare. > > (arm_output_iwmmxt_tinsr): Likewise. > > * config/arm/iwmmxt.md (WCGR0, WCGR1, WCGR2, WCGR3): New > > constant. > > (iwmmxt_psadbw, iwmmxt_walign, iwmmxt_tmrc, iwmmxt_tmcr): > > Delete. > > (rorv4hi3, rorv2si3, rordi3): Likewise. > > (rorv4hi3_di, rorv2si3_di, rordi3_di): Likewise. > > (ashrv4hi3_di, ashrv2si3_di, ashrdi3_di): Likewise. > > (lshrv4hi3_di, lshrv2si3_di, lshrdi3_di): Likewise. > > (ashlv4hi3_di, ashlv2si3_di, ashldi3_di): Likewise. > > (iwmmxt_tbcstqi, iwmmxt_tbcsthi, iwmmxt_tbcstsi): Likewise > > (*iwmmxt_clrv8qi, *iwmmxt_clrv4hi, *iwmmxt_clrv2si): Likewise. > > (tbcstv8qi, tbcstv4hi, tbsctv2si): New pattern. > > (iwmmxt_clrv8qi, iwmmxt_clrv4hi, iwmmxt_clrv2si): Likewise. > > (*and<mode>3_iwmmxt, *ior<mode>3_iwmmxt, *xor<mode>3_iwmmxt): > > Likewise. > > (ror<mode>3, ror<mode>3_di): Likewise. > > (ashr<mode>3_di, lshr<mode>3_di, ashl<mode>3_di): Likewise. > > (ashli<mode>3_iwmmxt, iwmmxt_waligni, iwmmxt_walignr): Likewise. > > (iwmmxt_walignr0, iwmmxt_walignr1): Likewise. > > (iwmmxt_walignr2, iwmmxt_walignr3): Likewise. > > (iwmmxt_setwcgr0, iwmmxt_setwcgr1): Likewise. > > (iwmmxt_setwcgr2, iwmmxt_setwcgr3): Likewise. > > (iwmmxt_getwcgr0, iwmmxt_getwcgr1): Likewise. > > (iwmmxt_getwcgr2, iwmmxt_getwcgr3): Likewise. > > (All instruction patterns): Add wtype attribute. > > (*iwmmxt_arm_movdi, *iwmmxt_movsi_insn): iWMMXt coexist with vfp. > > (iwmmxt_uavgrndv8qi3, iwmmxt_uavgrndv4hi3): Revise the pattern. > > (iwmmxt_uavgv8qi3, iwmmxt_uavgv4hi3): Likewise. > > (ashr<mode>3_iwmmxt, ashl<mode>3_iwmmxt, lshr<mode>3_iwmmxt): > > Likewise. > > (iwmmxt_tinsrb, iwmmxt_tinsrh, iwmmxt_tinsrw):Likewise. > > (eqv8qi3, eqv4hi3, eqv2si3, gtuv8qi3): Likewise. > > (gtuv4hi3, gtuv2si3, gtv8qi3, gtv4hi3, gtv2si3): Likewise. > > (iwmmxt_wunpckihh, iwmmxt_wunpckihw, iwmmxt_wunpckilh): Likewise. > > (iwmmxt_wunpckilw, iwmmxt_wunpckehub, iwmmxt_wunpckehuh): > > Likewise. > > (iwmmxt_wunpckehuw, iwmmxt_wunpckehsb, iwmmxt_wunpckehsh): > > Likewise. > > (iwmmxt_wunpckehsw, iwmmxt_wunpckelub, iwmmxt_wunpckeluh): > > Likewise. > > (iwmmxt_wunpckeluw, iwmmxt_wunpckelsb, iwmmxt_wunpckelsh): > > Likewise. > > (iwmmxt_wunpckelsw, iwmmxt_wmadds, iwmmxt_wmaddu): Likewise. > > (iwmmxt_wsadb, iwmmxt_wsadh, iwmmxt_wsadbz, iwmmxt_wsadhz): > > Likewise. > > (iwmmxt2.md): Include. > > * config/arm/iwmmxt2.md: New file. > > * config/arm/iterators.md (VMMX2): New mode_iterator. > > * config/arm/arm.md (wtype): New attribute. > > (UNSPEC_WMADDS, UNSPEC_WMADDU): Delete. > > (UNSPEC_WALIGNI): New unspec. > > * config/arm/t-arm (MD_INCLUDES): Add iwmmxt2.md. > > * config/arm/predicates.md (imm_or_reg_operand): New predicate. > > > > Thanks, > > Xinyu
