> -----Original Message-----
> From: Tamar Christina <tamar.christ...@arm.com>
> Sent: Wednesday, November 10, 2021 12:09 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd <n...@arm.com>; Richard Earnshaw <richard.earns...@arm.com>;
> Marcus Shawcroft <marcus.shawcr...@arm.com>; Kyrylo Tkachov
> <kyrylo.tkac...@arm.com>; Richard Sandiford
> <richard.sandif...@arm.com>
> Subject: [PATCH]AArch64 Remove shuffle pattern for rounding variant.
>
> Hi All,
>
> This removed the patterns to optimize the rounding shift and narrow.
> The optimization is valid only for the truncating rounding shift and narrow,
> for the rounding shift and narrow we need a different pattern that I will
> submit
> separately.
>
> This wasn't noticed before as the benchmarks did not run conformance as
> part of
> the run, which we now do and this now passes again.
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>
> Ok for master?
Ok.
Thanks,
Kyrill
>
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md
> (*aarch64_topbits_shuffle<mode>_le
> ,*aarch64_topbits_shuffle<mode>_be): Remove.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/shrn-combine-8.c: Update.
> * gcc.target/aarch64/shrn-combine-9.c: Update.
>
> --- inline copy of patch --
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index
> bff76e4b6e97db2613ab0ce1d721bf1828f0671b..c71658e2bf52b26bf9fc9fa70
> 2dd5446447f4d43 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -1887,22 +1887,6 @@ (define_insn
> "*aarch64_<srn_op>topbits_shuffle<mode>_le"
> [(set_attr "type" "neon_permute<q>")]
> )
>
> -(define_insn "*aarch64_topbits_shuffle<mode>_le"
> - [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
> - (vec_concat:<VNARROWQ2>
> - (unspec:<VNARROWQ> [
> - (match_operand:VQN 1 "register_operand" "w")
> - (match_operand:VQN 2
> "aarch64_simd_shift_imm_vec_exact_top")
> - ] UNSPEC_RSHRN)
> - (unspec:<VNARROWQ> [
> - (match_operand:VQN 3 "register_operand" "w")
> - (match_dup 2)
> - ] UNSPEC_RSHRN)))]
> - "TARGET_SIMD && !BYTES_BIG_ENDIAN"
> - "uzp2\\t%0.<V2ntype>, %1.<V2ntype>, %3.<V2ntype>"
> - [(set_attr "type" "neon_permute<q>")]
> -)
> -
> (define_insn "*aarch64_<srn_op>topbits_shuffle<mode>_be"
> [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
> (vec_concat:<VNARROWQ2>
> @@ -1917,22 +1901,6 @@ (define_insn
> "*aarch64_<srn_op>topbits_shuffle<mode>_be"
> [(set_attr "type" "neon_permute<q>")]
> )
>
> -(define_insn "*aarch64_topbits_shuffle<mode>_be"
> - [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
> - (vec_concat:<VNARROWQ2>
> - (unspec:<VNARROWQ> [
> - (match_operand:VQN 3 "register_operand" "w")
> - (match_operand:VQN 2
> "aarch64_simd_shift_imm_vec_exact_top")
> - ] UNSPEC_RSHRN)
> - (unspec:<VNARROWQ> [
> - (match_operand:VQN 1 "register_operand" "w")
> - (match_dup 2)
> - ] UNSPEC_RSHRN)))]
> - "TARGET_SIMD && BYTES_BIG_ENDIAN"
> - "uzp2\\t%0.<V2ntype>, %1.<V2ntype>, %3.<V2ntype>"
> - [(set_attr "type" "neon_permute<q>")]
> -)
> -
> (define_expand "aarch64_shrn<mode>"
> [(set (match_operand:<VNARROWQ> 0 "register_operand")
> (truncate:<VNARROWQ>
> diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-8.c
> b/gcc/testsuite/gcc.target/aarch64/shrn-combine-8.c
> index
> 6a47f3cdaee399e603c57a1c6a0c09c6cfd21abb..c93c179632156c07f05e6067e
> 63804db35cc436b 100644
> --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-8.c
> +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-8.c
> @@ -6,7 +6,7 @@
>
> uint8x16_t foo (uint16x8_t a, uint16x8_t b)
> {
> - return vrshrn_high_n_u16 (vrshrn_n_u16 (a, 8), b, 8);
> + return vshrn_high_n_u16 (vshrn_n_u16 (a, 8), b, 8);
> }
>
> /* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-9.c
> b/gcc/testsuite/gcc.target/aarch64/shrn-combine-9.c
> index
> 929a55c5c338844e6a5c5ad249af482286ab9c61..bdb3c13e5a2f89d62b6a24c2
> abe3535656399cac 100644
> --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-9.c
> +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-9.c
> @@ -6,7 +6,7 @@
>
> uint16x8_t foo (uint32x4_t a, uint32x4_t b)
> {
> - return vrshrn_high_n_u32 (vrshrn_n_u32 (a, 16), b, 16);
> + return vshrn_high_n_u32 (vshrn_n_u32 (a, 16), b, 16);
> }
>
> /* { dg-final { scan-assembler-times {\tuzp2\t} 1 } } */
>
>
> --
