On Mon, Nov 01, 2021 at 08:27:12AM +0100, Uros Bizjak wrote:
> > Also, I wonder for all these patterns (previously and now added), shouldn't
> > they have && TARGET_64BIT in conditions? I mean, we don't really support
> > scalar TImode for ia32, but VALID_SSE_REG_MODE includes V1TImode and while
> > the constant shifts can be done, I think the variable shifts can't, there
> > are no TImode shift patterns...
>
> - (match_operand:SI 2 "const_int_operand")))]
> - "TARGET_SSE2"
> + (match_operand:QI 2 "general_operand")))]
> + "TARGET_SSE2 && TARGET_64BIT"
>
> I wonder if this change is too restrictive, as it disables V1TI shifts
> by constant on 32bit targets. Perhaps we can introduce a conditional
> predicate, like:
>
> (define_predicate "shiftv1ti_input_operand"
> (if_then_else (match_test "TARGET_64BIT")
> (match_operand 0 "general_operand")
> (match_operand 0 "const_int_operand")))
>
> However, I'm not familiar with how the middle-end behaves with the
> above approach - will it try to put the constant in a register under
> some circumstances and consequently fail the expansion?
That would run again into the assertions that shift expanders must never
fail.
The question is if a V1TImode shift can ever appear in 32-bit x86, because
typedef __int128 V __attribute__((vector_size (16)));
is rejected with
error: ‘__int128’ is not supported on this target
when -m32 is in use, no matter what ISA flags are used.
Jakub
