On Thu, Oct 28, 2021 at 02:24:23PM +0200, Richard Biener wrote:
> I'm not able to trigger unsigned_float to be used, even when
> converting 0x8000000000000001 I get (float:DF (reg:DI...))
> on x86_64 because we emit conditional code that will end up
> using some compensation to emulate unsigned_float with
> float with some tricks that do not necessarily look safe
> from a rounding perspective (so maybe x86 would need to
> resort to soft-fp here?):
>
> movabsq $4611686018427387905, %rax
> cvtsi2sdq %rax, %xmm0
> addsd %xmm0, %xmm0
> ucomisd .LC0(%rip), %xmm0
>
> the constant is (0x8000000000000001u >> 1) | 1
Missing -mavx512f ?
(define_expand "floatunsdidf2"
[(set (match_operand:DF 0 "register_operand")
(unsigned_float:DF
(match_operand:DI 1 "nonimmediate_operand")))]
"((TARGET_64BIT && TARGET_AVX512F)
|| TARGET_KEEPS_VECTOR_ALIGNED_STACK)
&& TARGET_SSE2 && TARGET_SSE_MATH"
{
if (!TARGET_64BIT)
{
ix86_expand_convert_uns_didf_sse (operands[0], operands[1]);
DONE;
}
if (!TARGET_AVX512F)
{
x86_emit_floatuns (operands);
DONE;
}
})
where x86_emit_floatuns emits that emulation?
Anyway, what the testcase probably needs to do is this
(set (reg:DI temp1) (const_int ...))
(set (reg:DF temp2) (unsigned_float:DF (reg:DI temp1))) ! And also float
separately too
(set (reg:DI temp3) (subreg:DF (reg:DF temp2)))
or something similar so that during combine it is not rejected because
it is not valid to have the DFmode constants as immediates and they'd need
to go into memory instead. But the subreg might not be valid too.
So perhaps some different target.
Yet another option would be a self-test...
But if you don't have time for the testcase right now, let's just
handle it in UNSIGNED_FLOAT too and I can try to look at the testcase
later?
Jakub
