[committed] amdgcn: Fix assembler version incompatibility

[Andrew Stubbs]

I've committed this patch to fix another case of LLVM assembler 
incompatibility. Marcel previously posted a patch to fix up the 
global_load and global_store instructions, following a 
non-backwards-compatible change in the assembler.

https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572987.html
This patch fixes up another instance of the same problem, this time in 
the gather and scatter instruction patterns.

The fix is needed for LLVM 12 & 13. There is not change in behaviour for 
LLVM 9.

Andrewamdgcn: Fix assembler version incompatibility

This is another case of the global_load instruction format changing in LLVM
(because they fixed a bug).  The configure test is already in place to detect
what is needed.

gcc/ChangeLog:

        * config/gcn/gcn-valu.md (gather<mode>_insn_2offsets<exec>): Apply
        HAVE_GCN_ASM_GLOBAL_LOAD_FIXED.
        (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 84ff67508b99..01fdce64d423 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -827,8 +827,12 @@ (define_insn "gather<mode>_insn_2offsets<exec>"
        /* Work around assembler bug in which a 64-bit register is expected,
        but a 32-bit value would be correct.  */
        int reg = REGNO (operands[2]) - FIRST_VGPR_REG;
-       sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
-                     "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc);
+       if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED)
+         sprintf (buf, "global_load%%o0\t%%0, v%d, %%1 offset:%%3%s\;"
+                       "s_waitcnt\tvmcnt(0)", reg, glc);
+       else
+         sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
+                       "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc);
       }
     else
       gcc_unreachable ();
@@ -958,8 +962,12 @@ (define_insn "scatter<mode>_insn_2offsets<exec_scatter>"
        /* Work around assembler bug in which a 64-bit register is expected,
        but a 32-bit value would be correct.  */
        int reg = REGNO (operands[1]) - FIRST_VGPR_REG;
-       sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s",
-                reg, reg + 1, glc);
+       if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED)
+         sprintf (buf, "global_store%%s3\tv%d, %%3, %%0 offset:%%2%s",
+                  reg, glc);
+       else
+         sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s",
+                  reg, reg + 1, glc);
       }
     else
       gcc_unreachable ();