DImode is currently handled only for machines with vector modes
enabled, but this is unduly restrictive and is generally better done
in core registers.
gcc/ChangeLog:
PR target/102125
* config/arm/arm.md (movmisaligndi): New define_expand.
* config/arm/vec-common.md (movmisalign<mode>): Iterate over VDQ mode.
---
gcc/config/arm/arm.md | 16 ++++++++++++++++
gcc/config/arm/vec-common.md | 4 ++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5d3f21b91c4..4adc976b8b6 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -12617,6 +12617,22 @@ (define_expand "copysigndf3"
}"
)
+;; movmisalign for DImode
+(define_expand "movmisaligndi"
+ [(match_operand:DI 0 "general_operand")
+ (match_operand:DI 1 "general_operand")]
+ "unaligned_access"
+{
+ rtx lo_op0 = gen_lowpart (SImode, operands[0]);
+ rtx lo_op1 = gen_lowpart (SImode, operands[1]);
+ rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]);
+ rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]);
+
+ emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
+ emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
+ DONE;
+})
+
;; movmisalign patterns for HImode and SImode.
(define_expand "movmisalign<mode>"
[(match_operand:HSI 0 "general_operand")
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 68de4f0f943..e71d9b3811f 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -281,8 +281,8 @@ (define_expand "cml<fcmac1><conj_op><mode>4"
})
(define_expand "movmisalign<mode>"
- [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand")
- (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")]
+ [(set (match_operand:VDQ 0 "neon_perm_struct_or_reg_operand")
+ (unspec:VDQ [(match_operand:VDQ 1 "neon_perm_struct_or_reg_operand")]
UNSPEC_MISALIGNED_ACCESS))]
"ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN
&& unaligned_access && !TARGET_REALLY_IWMMXT"
