[PATCH] aarch64: Add smov alternative to sign_extend pattern

[Kyrylo Tkachov via Gcc-patches]

Hi all,

In the testcase here we were generating a umov + sxth to move
a half-word value from SIMD to GP regs with sign-extension.
We can use a single smov instruction for it instead but the
sign-extend pattern was missing the right alternative.
The *zero_extend<SHORT:mode><GPI:mode>2_aarch64 pattern for
zero-extension already has the right alternative for
the analogous umov instruction, so this mirrors that pattern.

Bootstrapped and tested on aarch64-none-linux-gnu.

The test gcc.target/aarch64/sve/clastb_4.c is adjusted to scan for
the clastb  h0, p0, h0, z0.h form
instead of
the clastb  w0, p0, w0, z0.h form.

This is an improvement as the W forms of the clast instructions are more 
expensive.

Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        * config/aarch64/aarch64.md (*extend<SHORT:mode><GPI:mode>2_aarch64):
        Add "r,w" alternative.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/smov_1.c: New test.
        * gcc.target/aarch64/sve/clastb_4.c: Adjust clast scan-assembler.

smov.patch
Description: smov.patch