The following patch attempts to resolve PR target/11877 (without
triggering PR/23102). On x86_64, writing an SImode or DImode zero
to memory uses an instruction encoding that is larger than first
clearing a register (using xor) then writing that to memory. Hence,
after reload, the peephole2 pass can determine if there's a suitable
free register, and if so, use that to shrink the code size with -Os.
To improve code size, and avoid inserting a large number of xor
instructions (PR target/23102), this patch makes use of peephole2's
efficient pattern matching to use a single temporary for a run of
consecutive writes. In theory, one could do better still with a
new target-specific pass, gated on -Os, to shrink these instructions
(like stv), but that's probably overkill for the little remaining
space savings.
Evaluating this patch on the CSiBE benchmark (v2.1.1) results in a
0.26% code size improvement (3715273 bytes down to 3705477) on x86_64
with -Os [saving 1 byte every 400]. 549 of 894 tests improve, two
tests grow larger. Analysis of these 2 pathological cases reveals
that although peephole2's match_scratch prefers to use a call-clobbered
register (to avoid requiring a new stack frame), very rarely this
interacts with GCC's shrink wrapping optimization, which may previously
have avoided saving/restoring a call clobbered register, such as %eax,
in the calling function.
This patch has been tested on x86_64-pc-linux-gnu with a make bootstrap
and make -k check with no new failures.
Ok for mainline?
2021-06-20 Roger Sayle <[email protected]>
gcc/ChangeLog
PR target/11877
* config/i386/i386.md: New define_peephole2s to shrink writing
1, 2 or 4 consecutive zeros to memory when optimizing for size.
gcc/testsuite/ChangeLog
PR target/11877
* gcc.target/i386/pr11877.c: New test case.
--
Roger Sayle
NextMove Software
Cambridge, UK
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 48532eb..2333261 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -19357,6 +19357,42 @@
ix86_expand_clear (operands[1]);
})
+;; When optimizing for size, zeroing memory should use a register.
+(define_peephole2
+ [(match_scratch:SWI48 0 "r")
+ (set (match_operand:SWI48 1 "memory_operand" "") (const_int 0))
+ (set (match_operand:SWI48 2 "memory_operand" "") (const_int 0))
+ (set (match_operand:SWI48 3 "memory_operand" "") (const_int 0))
+ (set (match_operand:SWI48 4 "memory_operand" "") (const_int 0))]
+ "optimize_insn_for_size_p () && peep2_regno_dead_p (0, FLAGS_REG)"
+ [(set (match_dup 1) (match_dup 0))
+ (set (match_dup 2) (match_dup 0))
+ (set (match_dup 3) (match_dup 0))
+ (set (match_dup 4) (match_dup 0))]
+{
+ ix86_expand_clear (operands[0]);
+})
+
+(define_peephole2
+ [(match_scratch:SWI48 0 "r")
+ (set (match_operand:SWI48 1 "memory_operand" "") (const_int 0))
+ (set (match_operand:SWI48 2 "memory_operand" "") (const_int 0))]
+ "optimize_insn_for_size_p () && peep2_regno_dead_p (0, FLAGS_REG)"
+ [(set (match_dup 1) (match_dup 0))
+ (set (match_dup 2) (match_dup 0))]
+{
+ ix86_expand_clear (operands[0]);
+})
+
+(define_peephole2
+ [(match_scratch:SWI48 0 "r")
+ (set (match_operand:SWI48 1 "memory_operand" "") (const_int 0))]
+ "optimize_insn_for_size_p () && peep2_regno_dead_p (0, FLAGS_REG)"
+ [(set (match_dup 1) (match_dup 0))]
+{
+ ix86_expand_clear (operands[0]);
+})
+
;; Reload dislikes loading constants directly into class_likely_spilled
;; hard registers. Try to tidy things up here.
(define_peephole2
/* PR target/11877 */
/* { dg-do compile } */
/* { dg-options "-Os" } */
void foo (long long *p)
{
*p = 0;
}
void bar (int *p)
{
*p = 0;
}
/* { dg-final { scan-assembler-times "xorl\[ \t\]" 2 } } */
/* { dg-final { scan-assembler-not "\\\$0," } } */
