On Thu, Jun 17, 2021 at 3:22 PM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> To generate sane code a SSE4.1 variable PBLENDV instruction is needed.
>
> 2021-06-17 Uroš Bizjak <ubiz...@gmail.com>
>
> gcc/
> PR target/97194
> * config/i386/i386-expand.c (expand_vector_set_var):
> Handle V2FS mode remapping. Pass TARGET_MMX_WITH_SSE to
> ix86_expand_vector_init_duplicate.
> (ix86_expand_vector_init_duplicate): Emit insv_1 for
> QImode for !TARGET_PARTIAL_REG_STALL.
> * config/i386/predicates.md (vec_setm_mmx_operand): New predicate.
> * config/i386/mmx.md (vec_setv2sf): Use vec_setm_mmx_operand
> as operand 2 predicate. Call ix86_expand_vector_set_var
> for non-constant index operand.
> (vec_setv2si): Ditto.
> (vec_setv4hi): Ditto.
> (vec_setv8qi): ditto.
>
> gcc/testsuite/
>
> PR target/97194
> * gcc.target/i386/sse4_1-vec-set-1.c: New test.
> * gcc.target/i386/sse4_1-vec-set-2.c: ditto.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Pushed to master.
Uros.
