I think the real problem is the expander name. That's why it could not be found
by optab. The second
mode needs to be the int vector mode of op3. With that change the testcases
work as expected:
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index c80d582a300d..ab605b3d2cf3 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -715,7 +715,7 @@
DONE;
})
-(define_expand "vcond_mask_<mode><mode>"
+(define_expand "vcond_mask_<mode><tointvec>"
[(set (match_operand:V 0 "register_operand" "")
(if_then_else:V
(eq (match_operand:<TOINTVEC> 3 "register_operand" "")
Ah, yes, it's indeed much simpler that way. Attached the revised
version with the small change and the new tests as a single patch now.
Regtest and bootstrap was successful.
Regards
Robin
>From 790feb49a6494c33f0fd4386a8148e0a4880e33b Mon Sep 17 00:00:00 2001
From: Robin Dapp <rd...@linux.ibm.com>
Date: Tue, 8 Jun 2021 11:49:26 +0200
Subject: [PATCH] s390: Add more vcond_mask patterns.
Add vcond_mask patterns that allow another mode for the condition/mask
than the source and target so e.g. boolean conditions become possible:
vtarget = bool_cond ? vsource1 : vsource2.
---
gcc/config/s390/vector.md | 2 +-
.../s390/vector/vcond-mixed-double.c | 41 +++++++++++++++++++
.../s390/vector/vcond-mixed-float.c | 41 +++++++++++++++++++
3 files changed, 83 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c
create mode 100644 gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index c80d582a300..ab605b3d2cf 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -715,7 +715,7 @@
DONE;
})
-(define_expand "vcond_mask_<mode><mode>"
+(define_expand "vcond_mask_<mode><tointvec>"
[(set (match_operand:V 0 "register_operand" "")
(if_then_else:V
(eq (match_operand:<TOINTVEC> 3 "register_operand" "")
diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c
new file mode 100644
index 00000000000..015bc8ab473
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c
@@ -0,0 +1,41 @@
+/* Check for vectorization of mixed conditionals. */
+/* { dg-do compile { target { s390*-*-* } } } */
+/* { dg-options "-O2 -march=z14 -mzarch -ftree-vectorize -fdump-tree-vect-details" } */
+
+double xd[1024];
+double zd[1024];
+double wd[1024];
+
+long xl[1024];
+long zl[1024];
+long wl[1024];
+
+void foold ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zd[i] = xl[i] ? zd[i] : wd[i];
+}
+
+void foodl ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zl[i] = xd[i] ? zl[i] : wl[i];
+}
+
+void foold2 ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zd[i] = (xd[i] > 0) ? zd[i] : wd[i];
+}
+
+void foold3 ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zd[i] = (xd[i] > 0. & wd[i] < 0.) ? zd[i] : wd[i];
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c
new file mode 100644
index 00000000000..ba40ffe8660
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c
@@ -0,0 +1,41 @@
+/* Check for vectorization of mixed conditionals. */
+/* { dg-do compile { target { s390*-*-* } } } */
+/* { dg-options "-O2 -march=z14 -mzarch -ftree-vectorize -fdump-tree-vect-details" } */
+
+float xf[1024];
+float zf[1024];
+float wf[1024];
+
+int xi[1024];
+int zi[1024];
+int wi[1024];
+
+void fooif ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zf[i] = xi[i] ? zf[i] : wf[i];
+}
+
+void foofi ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zi[i] = xf[i] ? zi[i] : wi[i];
+}
+
+void fooif2 ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zf[i] = (xf[i] > 0) ? zf[i] : wf[i];
+}
+
+void fooif3 ()
+{
+ int i;
+ for (i = 0; i < 1024; ++i)
+ zf[i] = (xf[i] > 0.f & wf[i] < 0.f) ? zf[i] : wf[i];
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */
--
2.23.0
