Hi!
On Tue, Mar 30, 2021 at 06:49:29PM -0500, Peter Bergner wrote:
> The mma_assemble_input_operand predicate does not accept reg+reg indexed
> addresses which can lead to ICEs. The problem is that the quad_address_p
> function only accepts reg+offset addresses that are valid for quad word
> accesses, but not reg+reg addresses which are also valid for quad word
> accesses when dealing with vector types. The solution used here is to
> call memory_operand, which uses rs6000_legitimate_address_p to ensure
> the address is valid. For reg+offset addresses, it uses quad_address_p like
> before, but for reg+reg addresses, it calls legitimate_indexed_address_p
> addresses which fixes this specific ICE.
quad_address_p should really only be used for lq/stq (and their prefixed
forms). Those insns have very different semantics: they are atomic,
while vector loads and stores are not; and the prefixed form has some
special semantics (it swaps halves on LE).
> diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
> index 859af75dfbd..e48c6eee19e 100644
> --- a/gcc/config/rs6000/predicates.md
> +++ b/gcc/config/rs6000/predicates.md
> @@ -1171,8 +1171,7 @@
> (define_special_predicate "mma_assemble_input_operand"
> (match_test "(mode == V16QImode
> && (vsx_register_operand (op, mode)
> - || (MEM_P (op)
> - && quad_address_p (XEXP (op, 0), mode, false))))"))
> + || memory_operand (op, mode)))"))
This seems like it might need reloads very often, because it allows way
too much? Or, can you just use reg_or_mem_operand?
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/powerpc/pr99842.C
> @@ -0,0 +1,188 @@
> +/* PR target/99842 */
> +/* { dg-require-effective-target power10_ok } */
> +/* { dg-options "-O3 -mdejagnu-cpu=power10 -w" } */
(Please document what warning you want to shut up. Just a few words is
plenty.)
That testcase will likely not show the error anymore just a year or so
from now, but it is good to have more complex testcases anyhow.
Segher
