[PATCH] aarch64: PR target/99822 Don't allow zero register in first operand of SUBS/ADDS-immediate

[Kyrylo Tkachov via Gcc-patches]

Hi all,

In this PR we end up generating an invalid instruction:
adds x1,xzr,#2

because the pattern accepts zero as an operand in the comparison, but the 
instruction doesn't.
Fix it by adjusting the predicate and constraints.

Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        PR target/99822
        * config/aarch64/aarch64.md (sub<mode>3_compare1_imm): Do not allow zero
        in operand 1.

gcc/testsuite/ChangeLog:

        PR target/99822
        * gcc.c-torture/compile/pr99822.c: New test.

zero-cmpimm.patch
Description: zero-cmpimm.patch