On Wed, Mar 24, 2021 at 11:32 PM Xionghu Luo <luo...@linux.ibm.com> wrote: > > On 2021/3/24 23:56, David Edelsohn wrote: > > On Wed, Mar 24, 2021 at 1:44 AM Xionghu Luo<luo...@linux.ibm.com> wrote: > >> l2 cache size for Power8 is 512kB, correct the copy paste error from > >> Power7. > >> Tested no performance change for SPEC2017. > >> > >> gcc/ChangeLog: > >> > >> 2021-03-24 Xionghu Luo<luo...@linux.ibm.com> > >> > >> * config/rs6000/rs6000.c (struct processor_costs): Change to > >> 512. > > This ChangeLog entry should state*what* you are changing to 512. > > > > BTW, the Power8 support was added before everything was public, so it > > used Power7 as the information that safely could be shared. The > > explanation in the ChangeLog probably should not characterize it as a > > "copy paste error". The value wasn't updated after the initial Power8 > > support was added. > > > > Okay with that change. > > > > Thanks for the information, committed to r11-7821-g08103e4d with the changes. > And backporting it to gcc-10 and eventually gcc-9?
Backport is okay. Thanks, David
