[committed] aarch64: Make aarch64_add_offset work with -ftrapv [PR99540]

[Richard Sandiford via Gcc-patches]

aarch64_add_offset uses expand_mult to multiply the SVE VL by an
out-of-range constant.  expand_mult takes an argument to indicate
whether the multiplication is signed or unsigned, but in this
context the multiplication is effectively signless and so the
choice seemed arbitrary.

However, one of the things that the signedness input does is
indicate whether signed overflow should be trapped for -ftrapv.
We don't want that here, so we must treat the multiplication
as unsigned.

Tested on aarch64-linux-gnu (with and without SVE).  Pushed to
trunk so far.  Will backport to GCC 10 tomorrow.

Richard


gcc/
2021-03-23  Jakub Jelinek  <ja...@redhat.com>

        PR target/99540
        * config/aarch64/aarch64.c (aarch64_add_offset): Tell
        expand_mult to perform an unsigned rather than a signed
        multiplication.

gcc/testsuite/
2021-03-23  Richard Sandiford  <richard.sandif...@arm.com>

        PR target/99540
        * gcc.dg/vect/pr99540.c: New test.
---
 gcc/config/aarch64/aarch64.c        |  2 +-
 gcc/testsuite/gcc.dg/vect/pr99540.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.dg/vect/pr99540.c

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index db69e6983d0..c8a87fe858a 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4639,7 +4639,7 @@ aarch64_add_offset (scalar_int_mode mode, rtx dest, rtx 
src,
          if (can_create_pseudo_p ())
            {
              rtx coeff1 = gen_int_mode (factor, mode);
-             val = expand_mult (mode, val, coeff1, NULL_RTX, false, true);
+             val = expand_mult (mode, val, coeff1, NULL_RTX, true, true);
            }
          else
            {
diff --git a/gcc/testsuite/gcc.dg/vect/pr99540.c 
b/gcc/testsuite/gcc.dg/vect/pr99540.c
new file mode 100644
index 00000000000..9136b099d94
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr99540.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-ftrapv -ffloat-store -march=armv8.2-a+sve" { 
target aarch64*-*-* } } */
+
+float *MSalign2m2m_rec_initverticalw, *MSalign2m2m_rec_currentw;
+
+void
+match_ribosum (int MSalign2m2m_rec_i, int MSalign2m2m_rec_lgth1,
+               int MSalign2m2m_rec_lgth2)
+{
+  float **WMMTX;
+
+  while (MSalign2m2m_rec_i < 1)
+    WMMTX[MSalign2m2m_rec_i++][0] = MSalign2m2m_rec_initverticalw[0];
+
+  while (MSalign2m2m_rec_i < MSalign2m2m_rec_lgth1)
+    MSalign2m2m_rec_initverticalw[MSalign2m2m_rec_i++] += 0.1;
+
+  while (MSalign2m2m_rec_i < MSalign2m2m_rec_lgth2)
+    MSalign2m2m_rec_currentw[MSalign2m2m_rec_i++] += 0.1;
+}