[PATCH] aarch64: Fix PR99437 - tighten shift predicates for narrowing shift patterns

Mon, 08 Mar 2021 07:04:51 -0800 

Hi all,

In this bug combine forms the (R)SHRN(2) instructions with an invalid shift 
amount.
The intrinsic expanders for these patterns validate the right shift amount but 
if the
final patterns end up being matched by combine (or other RTL passes I suppose) 
they
still let the wrong const_vector through.

This patch tightens up the predicates for the instructions involved by using 
predicates
for the right shift amount const_vectors.

Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        PR target/99437
        * config/aarch64/predicates.md (aarch64_simd_shift_imm_vec_qi): Define.
        (aarch64_simd_shift_imm_vec_hi): Likewise.
        (aarch64_simd_shift_imm_vec_si): Likewise.
        (aarch64_simd_shift_imm_vec_di): Likewise.
        * config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le): Use
        predicate from above.
        (aarch64_shrn<mode>_insn_be): Likewise.
        (aarch64_rshrn<mode>_insn_le): Likewise.
        (aarch64_rshrn<mode>_insn_be): Likewise.
        (aarch64_shrn2<mode>_insn_le): Likewise.
        (aarch64_shrn2<mode>_insn_be): Likewise.
        (aarch64_rshrn2<mode>_insn_le): Likewise.
        (aarch64_rshrn2<mode>_insn_be): Likewise.

gcc/testsuite/ChangeLog:

        PR target/99437
        * gcc.target/aarch64/simd/pr99437.c: New test.

Attachment: shrn-preds.patch
Description: shrn-preds.patch

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