Hi,
As subject, this patch rewrites [su]mull_high_n Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling and
optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-02-03 Jonathan Wright <jonathan.wri...@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add [su]mull_hi_n
builtin generator macros.
* config/aarch64/aarch64-simd.md
(aarch64_<su>mull_hi_n<mode>_insn): Define.
(aarch64_<su>mull_hi_n<mode>): Define.
* config/aarch64/arm_neon.h (vmull_high_n_s16): Use RTL builtin
instead of inline asm.
(vmull_high_n_s32): Likewise.
(vmull_high_n_u16): Likewise.
(vmull_high_n_u32): Likewise.
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index b787cb9788e758c1f103eab366b7aed4dc457830..4dac8e0d79bdf887e37e89f09c0beeeebbfd45aa 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -300,6 +300,9 @@
BUILTIN_VD_HSI (BINOP, smull_n, 0, NONE)
BUILTIN_VD_HSI (BINOPU, umull_n, 0, NONE)
+ BUILTIN_VQ_HSI (BINOP, smull_hi_n, 0, NONE)
+ BUILTIN_VQ_HSI (BINOPU, umull_hi_n, 0, NONE)
+
BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, NONE)
BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, NONE)
BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, NONE)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 393bab1920100badef21479b2f25cb6e1880c927..1d1ba379c28c052f53fc6c45573f3319ee5784f0 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2266,6 +2266,33 @@
[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
)
+(define_insn "aarch64_<su>mull_hi_n<mode>_insn"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (mult:<VWIDE>
+ (ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
+ (match_operand:VQ_HSI 1 "register_operand" "w")
+ (match_operand:VQ_HSI 3 "vect_par_cnst_hi_half" "")))
+ (ANY_EXTEND:<VWIDE>
+ (vec_duplicate:<VCOND>
+ (match_operand:<VEL> 2 "register_operand" "<h_con>")))))]
+ "TARGET_SIMD"
+ "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %2.<Vetype>[0]"
+ [(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
+)
+
+(define_expand "aarch64_<su>mull_hi_n<mode>"
+ [(match_operand:<VWIDE> 0 "register_operand")
+ (ANY_EXTEND:<VWIDE> (match_operand:VQ_HSI 1 "register_operand"))
+ (match_operand:<VEL> 2 "register_operand")]
+ "TARGET_SIMD"
+ {
+ rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
+ emit_insn (gen_aarch64_<su>mull_hi_n<mode>_insn (operands[0], operands[1],
+ operands[2], p));
+ DONE;
+ }
+)
+
;; vmlal_lane_s16 intrinsics
(define_insn "aarch64_vec_<su>mlal_lane<Qlane>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index d50bd65c497a02ea67c4aa02aff29f1ae7223b4e..fffd7b7bd2f7a3781f22cb6702b341d4318b1036 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -8275,48 +8275,28 @@ __extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmull_high_n_s16 (int16x8_t __a, int16_t __b)
{
- int32x4_t __result;
- __asm__ ("smull2 %0.4s,%1.8h,%2.h[0]"
- : "=w"(__result)
- : "w"(__a), "x"(__b)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_smull_hi_nv8hi (__a, __b);
}
__extension__ extern __inline int64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmull_high_n_s32 (int32x4_t __a, int32_t __b)
{
- int64x2_t __result;
- __asm__ ("smull2 %0.2d,%1.4s,%2.s[0]"
- : "=w"(__result)
- : "w"(__a), "w"(__b)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_smull_hi_nv4si (__a, __b);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmull_high_n_u16 (uint16x8_t __a, uint16_t __b)
{
- uint32x4_t __result;
- __asm__ ("umull2 %0.4s,%1.8h,%2.h[0]"
- : "=w"(__result)
- : "w"(__a), "x"(__b)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_umull_hi_nv8hi_uuu (__a, __b);
}
__extension__ extern __inline uint64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vmull_high_n_u32 (uint32x4_t __a, uint32_t __b)
{
- uint64x2_t __result;
- __asm__ ("umull2 %0.2d,%1.4s,%2.s[0]"
- : "=w"(__result)
- : "w"(__a), "w"(__b)
- : /* No clobbers */);
- return __result;
+ return __builtin_aarch64_umull_hi_nv4si_uuu (__a, __b);
}
__extension__ extern __inline poly16x8_t
