Hi Segher,
on 2020/12/15 下午10:40, Segher Boessenkool wrote:
> Hi Ke Wen,
>
> On Tue, Dec 15, 2020 at 03:53:29PM +0800, Kewen.Lin wrote:
>> on 2020/12/15 上午2:51, Segher Boessenkool wrote:
>>> On Wed, Dec 02, 2020 at 05:44:24PM +0800, Kewen.Lin wrote:
>>>> --- a/gcc/config/rs6000/rs6000.c
>>>> +++ b/gcc/config/rs6000/rs6000.c
>>>> @@ -6793,17 +6793,8 @@ rs6000_expand_vector_init (rtx target, rtx vals)
>>>> /* Force the values into word_mode registers. */
>>>> for (i = 0; i < n_elts; i++)
>>>> {
>>>> - rtx tmp = force_reg (GET_MODE_INNER (mode), XVECEXP (vals, 0, i));
>>>> - if (TARGET_POWERPC64)
>>>> - {
>>>> - op[i] = gen_reg_rtx (DImode);
>>>> - emit_insn (gen_zero_extendqidi2 (op[i], tmp));
>>>> - }
>>>> - else
>>>> - {
>>>> - op[i] = gen_reg_rtx (SImode);
>>>> - emit_insn (gen_zero_extendqisi2 (op[i], tmp));
>>>> - }
>>>> + rtx tmp = force_reg (inner_mode, XVECEXP (vals, 0, i));
>>>> + op[i] = simplify_gen_subreg (Pmode, tmp, inner_mode, 0);
>>>> }
>>>
>>> Pmode is defined based on TARGET_64BIT, not TARGET_POWERPC64.
>>
>> Good point, you are right, is it ok to change this part with one
>> explicit mode based on TARGET_POWERPC64?
>>
>> rtx tmp = force_reg (inner_mode, XVECEXP (vals, 0, i));
>> machine_mode tmode = TARGET_POWERPC64 ? DImode : SImode;
>> op[i] = simplify_gen_subreg (tmode, tmp, inner_mode, 0);
>
> That looks fine, yes.
>
>>> But, can you not always use SImode here?
>>
>> Sorry that I didn't quite follow here.
>
> I mean do
>
> rtx tmp = force_reg (inner_mode, XVECEXP (vals, 0, i));
> op[i] = simplify_gen_subreg (SImode, tmp, inner_mode, 0);
>
> If that works (also in 64-bit mode), that is preferred. It might need
> some more adjustment elsewhere, not sure if that is worth it.
>
Thanks for the clarification! Yes, as you said it doesn't work without
any adjustments, the gen_vsx_concat_v2di requires DImode operands, I
think it's not worthy to expand it just for this case.
> It is okay for trunk with either of those changes. Thanks!
>
Thanks! Committed with the former way via r11-6109.
BR,
Kewen
