When using the Solaris/x86 assembler with gcc, a couple of testcases
currently FAIL. Those failures follow two patterns:
FAIL: gcc.target/i386/avx512bw-vpmovb2m-2.c (test for excess errors)
Excess errors:
Assembler: avx512bw-vpmovb2m-2.c
"/var/tmp//ccPh3IRc.s", line 58 : Invalid instruction argument
Near line: " vpmovb2m %zmm0, %k0"
and
FAIL: gcc.target/i386/avx512dq-vreducesd-2.c (test for excess errors)
Excess errors:
Assembler: avx512dq-vreducesd-2.c
"/var/tmp//ccVyU7Bc.s", line 54 : Invalid instruction argument
Near line: " vreducesd $35, {sae}, %xmm0, %xmm0, %xmm7"
The first only started with
x86: relax mask register constraints
2019-01-04 Jan Beulich <[email protected]>
* config/i386/sse.md
(<avx512>_cmp<mode>3<mask_scalar_merge_name><round_saeonly_name>,
[...]
and is strange since even the current Intel 64 and IA-32 Architectures
Software Developer's Manual only lists %k1 for vpmovb2m and related
insns, and indeed the line assembles with %k0 changed to %k1.
The second is due to the use of {sae}: either this is a Solaris as bug
(the do claim AVX512DQ support) or they use a different syntax here:
omitting {sae} lets the line assemble as well.
To avoid those failures, I've extended the avx512bw and avx512dq
effective-target checks to include code snippets that trigger the
generation of those insns.
Tested no i386-pc-solaris2.11 with as (the failures are gone, as
expected) and gas (test results unchanged).
Ok for master?
Rainer
--
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University
2020-11-27 Rainer Orth <[email protected]>
gcc/testsuite:
* lib/target-supports.exp (check_effective_target_avx512dq): Add
_mm512_mask_reduce_round_ps.
(check_effective_target_avx512bw): Check for %k0 support.
Compile with -O2.
# HG changeset patch
# Parent ad34fb1f08c1a1948aeeb2466cbcd26e49753364
testsuite: i386: Extend effective-target checks for AVX512BW, AVX512DQ
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8805,6 +8805,10 @@ proc check_effective_target_sha { } {
proc check_effective_target_avx512dq { } {
return [check_no_compiler_messages avx512dq object {
typedef long long __v8di __attribute__ ((__vector_size__ (64)));
+ typedef float __m512 __attribute__ ((__vector_size__ (64)));
+ typedef float __v16sf __attribute__ ((__vector_size__ (64)));
+ typedef unsigned short __mmask16;
+
__v8di
_mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B)
{
@@ -8813,6 +8817,16 @@ proc check_effective_target_avx512dq { }
(__v8di) __W,
-1);
}
+
+ __m512
+ _mm512_mask_reduce_round_ps (__m512 __W, __mmask16 __U, __m512 __A, int __B,
+ const int __R)
+ {
+ return (__m512) __builtin_ia32_reduceps512_mask_round ((__v16sf) __A,
+ 0x23,
+ (__v16sf) __W,
+ 0xA6BA, 0x08);
+ }
} "-mavx512dq" ]
}
@@ -8821,6 +8835,11 @@ proc check_effective_target_avx512bw { }
return [check_no_compiler_messages avx512bw object {
typedef short __v32hi __attribute__ ((__vector_size__ (64)));
__v32hi
+ baz (__v32hi a)
+ {
+ return a == 0;
+ }
+ __v32hi
_mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B)
{
return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
@@ -8828,7 +8847,7 @@ proc check_effective_target_avx512bw { }
(__v32hi) __W,
-1);
}
- } "-mavx512bw" ]
+ } "-O2 -mavx512bw" ]
}
# Return 1 if avx512vp2intersect instructions can be compiled.
