On Mon, Nov 16, 2020 at 10:57 AM Philipp Tomsich <philipp.toms...@vrull.eu>
wrote:
> In case a negative shift operand makes it through into the backend,
> it will be treated as unsigned and truncated (using a mask) to fit
> into the range 0..31 (for SImode) and 0..63 (for DImode).
>
This is a de-optimization. This doesn't make any sense. The ISA manual
clearly states the shift counts are truncated. Some targets do this with
SHIFT_COUNT_TRUNCATED, but that is known to cause problems, so the RISC-V
port is doing it in the shift expanders. I believe that other targets do
this too.
Also, note that replacing
slli a0, a0, 31
with
li a1, -1;
sll a0, a0, a1
doesn't change the operation performed. The shift count is still truncated
to 31, and so you get the exact same result from both code sequences. All
you have done is make the code bigger and slower which is undesirable.
Also note that the testcase has implementation defined results, so there is
no wrong answer here, and nothing wrong with what the RISC-V port is doing.
+/* { dg-final { scan-assembler "sll" } } */
>
I don't think that this will work as a grep for sll will also match slli.
You would need to add a space or tab or maybe both to the search string to
prevent matches with slli. Or alternatively use scan-assembler-not "slli"
which will match and fail for both slli and slliw.
Jim
