On Thu, Nov 12, 2020 at 2:59 PM Richard Biener
<richard.guent...@gmail.com> wrote:
> I'm not sure what best to do here, as said accepting "any" (integer) mode as
> input is desirable (SImode, DImode but eventually also smaller modes). How
> that can be best achieved I don't know.
FTR, attached patch *should* allow s390 and amdgcn to emit vec_set
with SImode variable index operand, but I was not able to test the
patch by myself.
Uros.
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 1820b91877a..02ba599c373 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -3863,12 +3863,17 @@ can_vec_set_var_idx_p (machine_mode vec_mode)
return false;
machine_mode inner_mode = GET_MODE_INNER (vec_mode);
+
rtx reg1 = alloca_raw_REG (vec_mode, LAST_VIRTUAL_REGISTER + 1);
rtx reg2 = alloca_raw_REG (inner_mode, LAST_VIRTUAL_REGISTER + 2);
- rtx reg3 = alloca_raw_REG (VOIDmode, LAST_VIRTUAL_REGISTER + 3);
enum insn_code icode = optab_handler (vec_set_optab, vec_mode);
+ const struct insn_data_d *data = &insn_data[icode];
+ machine_mode idx_mode = data->operand[2].mode;
+
+ rtx reg3 = alloca_raw_REG (idx_mode, LAST_VIRTUAL_REGISTER + 3);
+
return icode != CODE_FOR_nothing && insn_operand_matches (icode, 0, reg1)
&& insn_operand_matches (icode, 1, reg2)
&& insn_operand_matches (icode, 2, reg3);
