HI Andrea, > -----Original Message----- > From: Andrea Corallo <andrea.cora...@arm.com> > Sent: 02 November 2020 09:03 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com>; Richard Earnshaw > <richard.earns...@arm.com>; nd <n...@arm.com> > Subject: [PATCH 5/x] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics > > Hi all, > > 5th patch of the serie here adding vld2_lane_bf16, vld2q_lane_bf16, > vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16, vld4q_lane_bf16 > related neon intrinsics. > > Please see refer to: > ACLE <https://developer.arm.com/docs/101028/latest> > ISA <https://developer.arm.com/docs/ddi0596/latest> > > Regtested and bootstrapped. > > Thanks! > > Andrea > > gcc/ChangeLog > > 2020-10-29 Andrea Corallo <andrea.cora...@arm.com> > > * config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16) > (vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16) > (vld4q_lane_bf16): Add intrinsics. > * config/arm/arm_neon_builtins.def: Touch for: > __builtin_neon_vld2_lanev4bf, __builtin_neon_vld2_lanev8bf, > __builtin_neon_vld3_lanev4bf, __builtin_neon_vld3_lanev8bf, > __builtin_neon_vld4_lanev4bf, __builtin_neon_vld4_lanev8bf. > * config/arm/iterators.md (VQ_HS): Add V8BF to the iterator. >
I think this part: diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index c70e3bc2731..8c0884518df 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -116,7 +116,7 @@ (define_mode_iterator VQ2BF [V16QI V8HI V8HF (V8BF "TARGET_BF16_SIMD") V4SI V4SF]) ;; Quad-width vector modes with 16- or 32-bit elements -(define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF]) +(define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF V8BF]) The V8BF needs to be guarded like so (V8BF "TARGET_BF16_SIMD") to make sure it's not enabled when bfloat16 is not available. Ok with that change. Thanks, Kyrill > gcc/testsuite/ChangeLog > > 2020-10-29 Andrea Corallo <andrea.cora...@arm.com> > > * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_bf16_indices_1.c: > Run it also for the arm backend. > * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_bf16_indices_1.c: > Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_bf16_indices_1.c: > Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_bf16_indices_1.c: > Likewise. > * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_bf16_indices_1.c: > Likewise. > * gcc.target/arm/simd/vldn_lane_bf16_1.c: New test.
