On Mon, Nov 2, 2020 at 12:31 PM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> On Mon, Nov 2, 2020 at 9:29 PM Uros Bizjak <ubiz...@gmail.com> wrote:
> >
> > On Mon, Nov 2, 2020 at 8:24 PM H.J. Lu <hjl.to...@gmail.com> wrote:
> > >
> > > MMX emulation with SEE is implemented at MMX intrinsic level, not at MMX
> > > instruction level. _mm_maskmove_si64 intrinsic for "MASKMOVQ mm1, mm2"
> > > is emulated with __builtin_ia32_maskmovdqu. Since SSE "MASKMOVQ mm1, mm2"
> > > builtin function, __builtin_ia32_maskmovq, can't be emulated with XMM
> > > registers, make __builtin_ia32_maskmovq also require MMX instead of SSE
> > > only.
> > >
> > > gcc/
> > >
> > > PR target/97140
> > > * config/i386/i386-expand.c (ix86_expand_builtin): Require MMX
> > > for __builtin_ia32_maskmovq.
> > >
> > > gcc/testsuite/
> > >
> > > PR target/97140
> > > * gcc.target/i386/pr97140.c: New test.
> >
> > OK with a small nit below.
> >
> > Thanks,
> > Uros.
> >
> > > ---
> > > gcc/config/i386/i386-expand.c | 6 +++++-
> > > gcc/testsuite/gcc.target/i386/pr97140.c | 10 ++++++++++
> > > 2 files changed, 15 insertions(+), 1 deletion(-)
> > > create mode 100644 gcc/testsuite/gcc.target/i386/pr97140.c
> > >
> > > diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
> > > index 9d2eb7f0308..06d349535fd 100644
> > > --- a/gcc/config/i386/i386-expand.c
> > > +++ b/gcc/config/i386/i386-expand.c
> > > @@ -11074,7 +11074,11 @@ ix86_expand_builtin (tree exp, rtx target, rtx
> > > subtarget,
> > > == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
> > > && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
> > > isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
> > > - if ((bisa & OPTION_MASK_ISA_MMX) && !TARGET_MMX && TARGET_MMX_WITH_SSE)
> >
> > Please put some vertical space here and at the end of the following if
> > clause.
>
> Also, maybe put the fcode test (and the comment) at the end of this
> check, so it will be clear that IX86_BUILTIN_MASKMOVQ is an exception
> to the rule.
This is the patch I am checking in. The difference is
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 06d349535fd..f479466e8f0 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -11074,15 +11074,17 @@ ix86_expand_builtin (tree exp, rtx target,
rtx subtarget,
== (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
&& (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
- /* NB: __builtin_ia32_maskmovq requires MMX. */
- if (fcode != IX86_BUILTIN_MASKMOVQ
- && (bisa & OPTION_MASK_ISA_MMX)
+
+ if ((bisa & OPTION_MASK_ISA_MMX)
&& !TARGET_MMX
- && TARGET_MMX_WITH_SSE)
+ && TARGET_MMX_WITH_SSE
+ /* NB: __builtin_ia32_maskmovq also requires MMX. */
+ && fcode != IX86_BUILTIN_MASKMOVQ)
{
bisa &= ~OPTION_MASK_ISA_MMX;
bisa |= OPTION_MASK_ISA_SSE2;
}
+
if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
{
bool add_abi_p = bisa & OPTION_MASK_ISA_64BIT;
Thanks.
--
H.J.
From a5016328626f73f901ebc23ec2f75871d0c5472a Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.to...@gmail.com>
Date: Mon, 21 Sep 2020 05:33:46 -0700
Subject: [PATCH] x86: Also require MMX for __builtin_ia32_maskmovq
MMX emulation with SEE is implemented at MMX intrinsic level, not at MMX
instruction level. _mm_maskmove_si64 intrinsic for "MASKMOVQ mm1, mm2"
is emulated with __builtin_ia32_maskmovdqu. Since SSE "MASKMOVQ mm1, mm2"
builtin function, __builtin_ia32_maskmovq, can't be emulated with XMM
registers, make __builtin_ia32_maskmovq also require MMX instead of SSE
only.
gcc/
PR target/97140
* config/i386/i386-expand.c (ix86_expand_builtin): Require MMX
for __builtin_ia32_maskmovq.
gcc/testsuite/
PR target/97140
* gcc.target/i386/pr97140.c: New test.
---
gcc/config/i386/i386-expand.c | 8 +++++++-
gcc/testsuite/gcc.target/i386/pr97140.c | 10 ++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr97140.c
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 9d2eb7f0308..f479466e8f0 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -11074,11 +11074,17 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
== (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
&& (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
- if ((bisa & OPTION_MASK_ISA_MMX) && !TARGET_MMX && TARGET_MMX_WITH_SSE)
+
+ if ((bisa & OPTION_MASK_ISA_MMX)
+ && !TARGET_MMX
+ && TARGET_MMX_WITH_SSE
+ /* NB: __builtin_ia32_maskmovq also requires MMX. */
+ && fcode != IX86_BUILTIN_MASKMOVQ)
{
bisa &= ~OPTION_MASK_ISA_MMX;
bisa |= OPTION_MASK_ISA_SSE2;
}
+
if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
{
bool add_abi_p = bisa & OPTION_MASK_ISA_64BIT;
diff --git a/gcc/testsuite/gcc.target/i386/pr97140.c b/gcc/testsuite/gcc.target/i386/pr97140.c
new file mode 100644
index 00000000000..edb39d916ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr97140.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-mmx -Wno-psabi" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+void
+_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
+{
+ __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); /* { dg-error "needs isa option -msse -m3dnowa -mmmx" } */
+}
--
2.28.0
