Hi Kyrylo, > ________________________________________ > From: Kyrylo Tkachov <kyrylo.tkac...@arm.com> > Sent: Thursday, October 22, 2020 9:40 AM > To: Dennis Zhang; gcc-patches@gcc.gnu.org > Cc: nd; Richard Earnshaw; Ramana Radhakrishnan > Subject: RE: [PATCH][Arm] Auto-vectorization for MVE: vsub > > Hi Dennis, > > > -----Original Message----- > > From: Dennis Zhang <dennis.zh...@arm.com> > > Sent: 06 October 2020 17:47 > > To: gcc-patches@gcc.gnu.org > > Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com>; nd <n...@arm.com>; > > Richard Earnshaw <richard.earns...@arm.com>; Ramana Radhakrishnan > > <ramana.radhakrish...@arm.com> > > Subject: Re: [PATCH][Arm] Auto-vectorization for MVE: vsub > > > > Hi all, > > > > On 8/17/20 6:41 PM, Dennis Zhang wrote: > > > > > > Hi all, > > > > > > This patch enables MVE vsub instructions for auto-vectorization. > > > It adds RTL templates for MVE vsub instructions using 'minus' instead of > > > unspec expression to make the instructions recognizable for vectorization. > > > MVE target is added in sub<mode>3 optab. The sub<mode>3 optab is > > > modified to use a mode iterator that selects available modes for various > > > targets correspondingly. > > > MVE vector modes are enabled in arm_preferred_simd_mode in arm.c to > > > support vectorization. > > > > > > This patch also fixes 'vreinterpretq_*.c' MVE intrinsic tests. The tests > > > generate wrong instruction numbers because of unexpected icf > > optimization. > > > This bug is exposed by the MVE vector modes enabled in this patch, > > > therefore it is corrected in this patch to avoid test failures. > > > > > > MVE instructions are documented here: > > > https://developer.arm.com/architectures/instruction-sets/simd- > > isas/helium/helium-intrinsics > > > > > > The patch is regtested for arm-none-eabi and bootstrapped for > > > arm-none-linux-gnueabihf. > > > > > > Is it OK for trunk please? > > > > > > Thanks > > > Dennis > > > > > > gcc/ChangeLog: > > > > > > 2020-08-10 Dennis Zhang <dennis.zh...@arm.com> > > > > > > * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE vector > > modes. > > > * config/arm/arm.h (TARGET_NEON_IWMMXT): New macro. > > > (TARGET_NEON_IWMMXT_MVE, TARGET_NEON_IWMMXT_MVE_FP): > > Likewise. > > > (TARGET_NEON_MVE_HFP): Likewise. > > > * config/arm/iterators.md (VSEL): New mode iterator to select modes > > > for corresponding targets. > > > * config/arm/mve.md (mve_vsubq<mode>): New entry for vsub instruction > > > using expression 'minus'. > > > (mve_vsubq_f<mode>): Use minus instead of VSUBQ_F unspec. > > > * config/arm/neon.md (sub<mode>3): Removed here. Integrated in the > > > sub<mode>3 in vec-common.md > > > * config/arm/vec-common.md (sub<mode>3): Enable MVE target. Use > > VSEL > > > to select available modes. Exclude TARGET_NEON_FP16INST from > > > TARGET_NEON statement. Intergrate TARGET_NEON_FP16INST which is > > > originally in neon.md. > > > > > > gcc/testsuite/ChangeLog: > > > > > > 2020-08-10 Dennis Zhang <dennis.zh...@arm.com> > > > > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional > > > option -fno-ipa-icf and change the instruction count from 8 to 16. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. > > > * gcc.target/arm/mve/mve.exp: Include tests in subdir 'vect'. > > > * gcc.target/arm/mve/vect/vect_sub_0.c: New test. > > > * gcc.target/arm/mve/vect/vect_sub_1.c: New test. > > > > > > > This patch is updated based on Richard Sandiford's patch adding new > > vector mode macros: > > https://gcc.gnu.org/pipermail/gcc-patches/2020-September/553425.html > > The old version of this patch is at > > https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html > > And a less related part in the old version is separated into another > > patch: https://gcc.gnu.org/pipermail/gcc-patches/2020- > > September/554100.html > > > > This patch enables MVE vsub instructions for auto-vectorization. > > It adds insns for MVE vsub instructions using 'minus' instead of unspec > > expression to make the instructions recognizable for auto-vectorization. > > The sub<mode>3 in mve.md is modified to use new mode macros which > > make > > the expander available when certain modes are supported. Then various > > targets can share this expander for vectorization. The redundant > > sub<mode>3 insns in neon.md are then removed. > > > > Regression tested on arm-none-eabi and bootstraped on > > arm-none-linux-gnueabihf. > > > > Is it OK for trunk please? > > Ok. > Thanks, > Kyrill >
Thanks for your approval. The patch has been committed as 98161c248c88f873bbffba23664c540f551d89d5 Bests Dennis > > > > gcc/ChangeLog: > > > > 2020-10-02 Dennis Zhang <dennis.zh...@arm.com> > > > > * config/arm/mve.md (mve_vsubq<mode>): New entry for vsub instruction > > using expression 'minus'. > > (mve_vsubq_f<mode>): Use minus instead of VSUBQ_F unspec. > > * config/arm/neon.md (*sub<mode>3_neon): Use the new mode macros > > ARM_HAVE_<MODE>_ARITH. > > (sub<mode>3, sub<mode>3_fp16): Removed. > > (neon_vsub<mode>): Use gen_sub<mode>3 instead of > > gen_sub<mode>3_fp16. > > * config/arm/vec-common.md (sub<mode>3): Use the new mode macros > > ARM_HAVE_<MODE>_ARITH. > > > > gcc/testsuite/ChangeLog: > > > > 2020-10-02 Dennis Zhang <dennis.zh...@arm.com> > > > > * gcc.target/arm/simd/mve-vsub_1.c: New test. > >
