Alex Coplan <alex.cop...@arm.com> writes:
> @@ -11707,32 +11638,12 @@ aarch64_branch_cost (bool speed_p, bool
> predictable_p)
> /* Return true if the RTX X in mode MODE is a zero or sign extract
> usable in an ADD or SUB (extended register) instruction. */
> static bool
> -aarch64_rtx_arith_op_extract_p (rtx x, scalar_int_mode mode)
> -{
> - /* Catch add with a sign extract.
> - This is add_<optab><mode>_multp2. */
> - if (GET_CODE (x) == SIGN_EXTRACT
> - || GET_CODE (x) == ZERO_EXTRACT)
> - {
> - rtx op0 = XEXP (x, 0);
> - rtx op1 = XEXP (x, 1);
> - rtx op2 = XEXP (x, 2);
> -
> - if (GET_CODE (op0) == MULT
> - && CONST_INT_P (op1)
> - && op2 == const0_rtx
> - && CONST_INT_P (XEXP (op0, 1))
> - && aarch64_is_extend_from_extract (mode,
> - XEXP (op0, 1),
> - op1))
> - {
> - return true;
> - }
> - }
> +aarch64_rtx_arith_op_extract_p (rtx x)
> +{
> /* The simple case <ARITH>, XD, XN, XM, [us]xt.
> No shift. */
> - else if (GET_CODE (x) == SIGN_EXTEND
> - || GET_CODE (x) == ZERO_EXTEND)
> + if (GET_CODE (x) == SIGN_EXTEND
> + || GET_CODE (x) == ZERO_EXTEND)
> return REG_P (XEXP (x, 0));
>
> return false;
Didn't notice this last time, sorry, but:
s/the RTX X in mode MODE/X/
now that there's no longer a mode parameter.
OK with that change if 2/2 is approved.
Thanks,
Richard
