Hi!
On Sun, Oct 04, 2020 at 09:56:01PM -0400, Hans-Peter Nilsson wrote:
> Please excuse a comment from the gallery:
>
> On Mon, 28 Sep 2020, will schmidt via Gcc-patches wrote:
> > On Fri, 2020-09-04 at 12:52 -0300, Raoni Fassina Firmino via Gcc-patches
> > wrote:
> > > +(define_expand "feraiseexceptsi"
> > > + [(use (match_operand:SI 1 "const_int_operand" "n"))
> > > + (set (match_operand:SI 0 "gpc_reg_operand")
> > > + (const_int 0))]
> > > + "TARGET_HARD_FLOAT"
> > > +{
> > > + switch (INTVAL (operands[1]))
> > > + {
> > > + case 0x2000000: /* FE_INEXACT */
> > > + case 0x4000000: /* FE_DIVBYZERO */
> > > + case 0x8000000: /* FE_UNDERFLOW */
> > > + case 0x10000000: /* FE_OVERFLOW */
> > > + break;
> > > + default:
> > > + FAIL;
> > > + }
> > > +
> > > + rtx tmp = gen_rtx_CONST_INT (SImode, __builtin_clz (INTVAL
> > > (operands[1])));
>
> This doesn't appear to be very portable, to any-cxx11-compiler
> that doesn't pretend to be gcc-intrinsics-compatible.
Yeah, very good point!
Should this pattern not allow setting more than one exception bit at
once, btw?
So you can first see if any out-of-range bits are set:
unsigned int fe = INTVAL (operands[1]);
if ((fe & 0x1e000000) != fe)
FAIL;
and then see if more than one bit is set:
if (fe & (fe - 1))
FAIL;
but also disallow zero:
if (!fe)
FAIL;
Or, you can just put the bit number in the switch cases for the four
bits. There are only four, after all.
Thanks,
Segher
