Hi!
On Mon, Aug 17, 2020 at 01:06:10PM +0200, Uros Bizjak wrote:
> On Mon, Aug 17, 2020 at 12:42 PM Roger Sayle <ro...@nextmovesoftware.com>
> wrote:
> > (insn 14 7 15 2 (set (reg/i:SI 0 ax)
> > (subreg:SI (reg:DI 84) 0)) "pr92180.c":5:1 67 {*movsi_internal}
> > (expr_list:REG_DEAD (reg:DI 84)
> > (nil)))
> >
> > Normally, combine/simplify-rtx would notice that insns 6 and 7
> > (which update highpart bits) are unnecessary as the final insn 14
> > only requires to lowpart bits. The complication is that insn 14
> > sets a hard register in targetm.class_likely_spilled_p which
> > prevents combine from performing its simplifications, and removing
> > the redundant instructions.
> I think that fwprop interferes with recent change to combine, where
> combine won't propagate hard registers anymore.
It won't propagate move insns from a hard non-fixed register to a
pseudo into other insns, yeah. But that does not apply here?
> So, following that
> change, there is no point for fwprop to create instructions that
> combine won't be able to process. Alternatively, perhaps fwprop should
> be prevented from propagating likely_spilled hard registers?
>
> Let's ask Segher for his opinion.
I have no opinion about class_likely_spilled_p; it is just a gross
target hack as far as I can see. (I wonder how much of that is still
useful with LRA?)
Maybe combine could move return values in a hard reg through a pseudo?
So pretty much the same as make_more_copies, but the other way around.
You'll get the copy to a pseudo (which is in SImode here) as a separate
insn that combines with the previous insns fine, and RA will give the
pseudo the same hard register in all cases where that is beneficial.
Segher
