Hi!
On Fri, Jun 26, 2020 at 01:20:43PM -0500, will schmidt wrote:
> * config/rs6000/altivec.h (vec_vmsumudm): New define.
> * config/rs6000/altivec.md (UNSPEC_VMSUMUDM): New unspec.
> (altivec_vmsumudm): New define_insn.
> * config/rs6000/rs6000-builtin.def (altivec_vmsumudm): New
> BU_ALTIVEC_3 entry. (vmsumudm): New BU_ALTIVEC_OVERLOAD_3
> entry.
> +(define_insn "altivec_vmsumudm"
> + [(set (match_operand:V1TI 0 "register_operand" "=v")
> + (unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v")
> + (match_operand:V2DI 2 "register_operand" "v")
> + (match_operand:V1TI 3 "register_operand" "v")]
> + UNSPEC_VMSUMUDM))]
> + "TARGET_P8_VECTOR"
> + "vmsumudm %0,%1,%2,%3"
> + [(set_attr "type" "veccomplex")])
I wonder if it would be better to actually describe what the insn does,
instead of using an unspec. All similar insns are like this already of
course, it's not something that needs to be fixed right now.
TARGET_P8_VECTOR is wrong (it is ISA 3.0B).
> +The @code{vec_msum} functions perform a vector multiply-sum, returning
> +the result of arg1*arg2+arg3. ISA 3.0 adds support for vec_msum returning
> +a vector int128 result.
Well, that doesn't describe the horizontal addition it does? The muls
are widening, and two adjacent results are added (together with the
corresponding elt in arg3).
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c
> @@ -0,0 +1,25 @@
> +/* Verify that overloaded built-ins for vec_msum with __int128
> + inputs generate the proper code. */
> +
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_p8vector_ok } */
> +/* { dg-options "-mdejagnu-cpu=power8 -O3" } */
This needs to change to power9 as well?
Thanks,
Segher
