From b23f14d42da014504fb8237ba71098a2db5c3123 Mon Sep 17 00:00:00 2001 From: z00512037 Date: Wed, 24 Jun 2020 22:48:45 +0800 Subject: [PATCH] store-merging: ICE in find_bswap_or_nop_1 PR95854. The patch add a judgement in find_bswap_or_nop_1 to make sure both operand1 and operand2 are INTEGER_CST. If not, it is not able to be converted to a unsigned HOST_WIDE_INT. gcc/ChangeLog: 2020-06-24 Kaipeng Zhou PR tree-optimization/95854 * gimple-ssa-store-merging.c: For find_bswap_or_nop_1, return NULL if operand 1 or 2 of stmt's rhs which is BIT_FIELD_REF are not INTEGER_CST. gcc/testsuite/ChangeLog: 2020-06-24 Kaipeng Zhou PR tree-optimization/95854 * testsuite/gcc.dg/pr95854.c: New test. --- gcc/ChangeLog | 7 +++++++ gcc/gimple-ssa-store-merging.c | 4 ++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr95854.c | 19 +++++++++++++++++++ 4 files changed, 35 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/pr95854.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index df8e512ae66..76d3b15bd4c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2020-06-24 Kaipeng Zhou + + PR tree-optimization/95854 + * gimple-ssa-store-merging.c: For find_bswap_or_nop_1, return NULL + if operand 1 or 2 of stmt's rhs which is BIT_FIELD_REF are not + INTEGER_CST. + 2020-06-22 Segher Boessenkool * config/rs6000/altivec.h: Use _ARCH_PWR10, not _ARCH_PWR_FUTURE. diff --git a/gcc/gimple-ssa-store-merging.c b/gcc/gimple-ssa-store-merging.c index 3ab614148a7..edb1c55f495 100644 --- a/gcc/gimple-ssa-store-merging.c +++ b/gcc/gimple-ssa-store-merging.c @@ -598,6 +598,10 @@ find_bswap_or_nop_1 (gimple *stmt, struct symbolic_number *n, int limit) if (TREE_CODE (rhs1) == BIT_FIELD_REF && TREE_CODE (TREE_OPERAND (rhs1, 0)) == SSA_NAME) { + if (TREE_CODE (TREE_OPERAND (rhs1, 1)) != INTEGER_CST + || TREE_CODE (TREE_OPERAND (rhs1, 2)) != INTEGER_CST) + return NULL; + unsigned HOST_WIDE_INT bitsize = tree_to_uhwi (TREE_OPERAND (rhs1, 1)); unsigned HOST_WIDE_INT bitpos = tree_to_uhwi (TREE_OPERAND (rhs1, 2)); if (bitpos % BITS_PER_UNIT == 0 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e1c78bcbd34..c4b2e09ad25 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-06-24 Kaipeng Zhou + + PR tree-optimization/95854 + * gcc.dg/pr95854.c: New test. + 2020-06-22 Segher Boessenkool * gcc.target/powerpc/cfuged-0.c: I protest. diff --git a/gcc/testsuite/gcc.dg/pr95854.c b/gcc/testsuite/gcc.dg/pr95854.c new file mode 100644 index 00000000000..651d747cd0b --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr95854.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.5-a+sve2 -fno-vect-cost-model -fno-tree-scev-cprop -ftracer" } */ + +extern void abort (void); +int c, d; +int main() +{ + int e[] = {4, 4, 4, 4, 4, 4, 4, 4, 4}; + d = 8; + for (; d; d--) + for (int a = 0; a <= 8; a++) + { + c = e[1]; + e[d] = 0; + } + if (c != 0) + abort (); + return 0; +} -- 2.19.1