On 29/05/2020 13:28, duanbo (C) wrote: > > >> -----Original Message----- >> From: Andrew Pinski [mailto:pins...@gmail.com] >> Sent: Monday, May 18, 2020 11:49 AM >> To: duanbo (C) <duan...@huawei.com> >> Cc: GCC Patches <gcc-patches@gcc.gnu.org> >> Subject: Re: [PATCH] aarch64: Change the definition of Pmode [pr95182] >> >> On Sun, May 17, 2020 at 8:23 PM duanbo (C) <duan...@huawei.com> wrote: >>> >>> Hi, >>> >>> This changes the definition of Pmode for aarch64 port. >>> Unlike x86, S390 etc., Pmode is always set to DImode for aarch64 port even >> under ILP32. >>> Because of that definition, machine mode of symbol_ref which is >> supposed to be SImode becomes DImode under target ILP32. >>> Definition of Pmode should depend on the current ABI, i.e., SImode for >> ILP32 and DImode for LP64. >>> Attached please find the proposed patch . >>> Bootstrap and tested on aarch64 Linux platform. No new regression >> witnessed. >>> Any suggestion? >> >> THIS DOES NOT WORK correctly and will never work correctly. When I was >> originally writing AARCH64 ILP32 (back in 2013), I went this route first (as >> it >> was the fastest way to get it working; I could not wait on ARM's >> implementation at the time) but I had regressions. >> >> The place where it fails was something like: >> int f(char *g, int t) >> { >> return g[t]; >> } >> >> Which you pass -1 for t as there would be no zero-extend any more. >> I remember at least one testcase in the testsuite failing due to >> implementation this way even; I don't remember which one as I did not write >> it down and it was over 6 years ago. >> >> If there was an arch mode which would VAs to be truncated to 32bits, this >> would be the correct way to implement this. >> >> The reason why the other ABIs/targets define Pmode as SImode is because >> the underlying hardware will extend the VA correctly as Linux will set the >> arch bit correctly (NOTE MIPS is an example where index'ed load/stores >> which has a similar issue even on MIPS32 but that is a different story). >> >> Also there are other ABIs where Pmode != PTRmode (e.g. IA64-HPUX32). >> x32 has an option which can select either way. The ISA on x86_64 supports >> both cases which is why it can be selected that way; this is unlike AARCH64 >> which cannot. >> >> Thanks, >> Andrew Pinski >> >>> >>> Thanks, >>> Duanbo > > Hi > > I got your point. The hardware of AARCH64 determines the definition of Pmode. > But I didn't figure out the reason why the other ABIs / targets could define > Pmode as SImode.
I don't know precisely, but I would imagine that on X86 (and maybe other architectures) this works because the 64-bit ISA is simply a superset of the the 32-bit ISA. So there are load and store operations that take a 32-bit base register for addresses and these can be used even when in 64-bit operational mode. On AArch64 we don't have that option as all registers used for addressing in the ISA are 64 bits in size. Ergo, our only option is to have Pmode=DImode. > There is not much information about ILP32 on the official website of ARM. > It would be very helpful if you can provide some useful documents, especially > the different hardware implementation between X86 and AARCH64 in this issue. > I really want to figure out. > thanks. > > Duanbo > R.
