2020-05-27 Uroš Bizjak <[email protected]>
gcc/ChangeLog:
PR target/95355
* config/i386/sse.md
(<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>):
Remove %q operand modifier from insn template.
(avx512f_<code>v8hiv8di2<mask_name>): Ditto.
gcc/testsuite/ChangeLog:
PR target/95355
* gcc.target/i386/pr95355.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index fde65391d7d..1cf1b8cea3b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -17559,7 +17559,7 @@
(any_extend:V16SI
(match_operand:V16QI 1 "nonimmediate_operand" "vm")))]
"TARGET_AVX512F"
- "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+ "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -17935,7 +17935,7 @@
(any_extend:V8DI
(match_operand:V8HI 1 "nonimmediate_operand" "vm")))]
"TARGET_AVX512F"
- "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+ "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
diff --git a/gcc/testsuite/gcc.target/i386/pr95355.c
b/gcc/testsuite/gcc.target/i386/pr95355.c
new file mode 100644
index 00000000000..3e4faba19f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95355.c
@@ -0,0 +1,20 @@
+/* PR target/95355 */
+/* { dg-do assemble { target avx512dq } } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-O -fno-tree-dominator-opts -fno-tree-fre
-ftree-slp-vectorize -fno-tree-ter -mavx512dq -masm=intel" } */
+
+typedef int __attribute__((__vector_size__(64))) U;
+typedef __int128 __attribute__((__vector_size__(32))) V;
+
+U i;
+V j;
+
+int
+foo(unsigned char l)
+{
+ V m = j % 999;
+ U n = l <= i;
+ V o = ((union { U a; V b[2]; }) n).b[0] + m;
+ return o[0];
+}