Now with a patch attached.
On Thu, May 14, 2020 at 9:18 AM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> gcc/ChangeLog:
>
> 2020-05-14 Uroš Bizjak <ubiz...@gmail.com>
>
> PR target/95046
> * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): rename from mmx_pf2id.
> Add SSE/AVX alternative. Change operand predicates from
> nonimmediate_operand to register_mmxmem_operand.
> Enable instruction pattern for TARGET_MMX_WITH_SSE.
> (fix_truncv2sfv2si2): New expander.
> (fixuns_truncv2sfv2si2): Ditto.
>
> (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
> Add SSE/AVX alternative. Change operand predicates from
> nonimmediate_operand to register_mmxmem_operand.
> Enable instruction pattern for TARGET_MMX_WITH_SSE.
> (floatv2siv2sf2): New expander.
> (floatunsv2siv2sf2): Ditto.
>
> * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
> Update for rename.
> (IX86_BUILTIN_PI2FD): Ditto.
>
> testsuite/ChangeLog:
>
> 2020-05-14 Uroš Bizjak <ubiz...@gmail.com>
>
> PR target/95046
> * gcc.target/i386/pr95046-5.c: New test.
>
> Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
>
> Uros.
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 4d1d7b5b0be..fa123788a8e 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -528,8 +528,8 @@ BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3,
"__builtin_ia32_psraw", I
BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad",
IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
/* 3DNow! */
-BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id",
IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF)
-BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_floatv2si2,
"__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI)
+BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_fix_truncv2sfv2si2,
"__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF)
+BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_floatv2siv2sf2,
"__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI)
BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_rcpv2sf2,
"__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF)
BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_rsqrtv2sf2,
"__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index d159134e0fb..2955ca2898f 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -777,14 +777,63 @@
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "mmx_pf2id"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pf2id\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
+(define_insn "mmx_fix_truncv2sfv2si2"
+ [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
+ (fix:V2SI (match_operand:V2SF 1 "register_mmxmem_operand" "ym,Yv")))]
+ "TARGET_3DNOW || TARGET_MMX_WITH_SSE"
+ "@
+ pf2id\t{%1, %0|%0, %1}
+ %vcvttps2dq\t{%1, %0|%0, %1}"
+ [(set_attr "isa" "*,sse2")
+ (set_attr "mmx_isa" "native,*")
+ (set_attr "type" "mmxcvt,ssecvt")
+ (set_attr "prefix_extra" "1,*")
+ (set_attr "prefix_rep" "*,1")
+ (set_attr "prefix_data16" "*,0")
+ (set_attr "prefix" "*,maybe_vex")
+ (set_attr "mode" "V2SF,TI")])
+
+(define_expand "fix_truncv2sfv2si2"
+ [(set (match_operand:V2SI 0 "register_operand")
+ (fix:V2SI (match_operand:V2SF 1 "register_operand")))]
+ "TARGET_MMX_WITH_SSE")
+
+(define_insn "fixuns_truncv2sfv2si2"
+ [(set (match_operand:V2SI 0 "register_operand" "=v")
+ (unsigned_fix:V2SI (match_operand:V2SF 1 "register_operand" "v")))]
+ "TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
+ "vcvttps2udq\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
+(define_insn "mmx_floatv2siv2sf2"
+ [(set (match_operand:V2SF 0 "register_operand" "=y,Yv")
+ (float:V2SF (match_operand:V2SI 1 "register_mmxmem_operand" "ym,Yv")))]
+ "TARGET_3DNOW || TARGET_MMX_WITH_SSE"
+ "@
+ pi2fd\t{%1, %0|%0, %1}
+ %vcvtdq2ps\t{%1, %0|%0, %1}"
+ [(set_attr "isa" "*,sse2")
+ (set_attr "mmx_isa" "native,*")
+ (set_attr "type" "mmxcvt,ssecvt")
(set_attr "prefix_extra" "1")
- (set_attr "mode" "V2SF")])
+ (set_attr "prefix" "*,maybe_vex")
+ (set_attr "mode" "V2SF,V4SF")])
+
+(define_expand "floatv2siv2sf2"
+ [(set (match_operand:V2SF 0 "register_operand")
+ (float:V2SF (match_operand:V2SI 1 "register_operand")))]
+ "TARGET_MMX_WITH_SSE")
+
+(define_insn "floatunsv2siv2sf2"
+ [(set (match_operand:V2SF 0 "register_operand" "=v")
+ (unsigned_float:V2SF (match_operand:V2SI 1 "register_operand" "v")))]
+ "TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
+ "vcvtudq2ps\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "V4SF")])
(define_insn "mmx_pf2iw"
[(set (match_operand:V2SI 0 "register_operand" "=y")
@@ -810,15 +859,6 @@
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
-(define_insn "mmx_floatv2si2"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pi2fd\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "prefix_extra" "1")
- (set_attr "mode" "V2SF")])
-
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Parallel single-precision floating point element swizzling
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-5.c
b/gcc/testsuite/gcc.target/i386/pr95046-5.c
new file mode 100644
index 00000000000..bff55ddef31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-5.c
@@ -0,0 +1,44 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -mavx512vl" } */
+
+
+float r[2];
+int s[2];
+unsigned int u[2];
+
+void
+test_float (void)
+{
+ for (int i = 0; i < 2; i++)
+ r[i] = s[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvtdq2ps" } } */
+
+void
+test_ufloat (void)
+{
+ for (int i = 0; i < 2; i++)
+ r[i] = u[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvtudq2ps" } } */
+
+void
+test_fix (void)
+{
+ for (int i = 0; i < 2; i++)
+ s[i] = r[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvttps2dq" } } */
+
+void
+test_ufix (void)
+{
+ for (int i = 0; i < 2; i++)
+ u[i] = r[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvttps2udq" } } */
