On Wed, Apr 22, 2020 at 10:31 AM Richard Sandiford
<richard.sandif...@arm.com> wrote:
>
> This is really PR94683 part 2, handling the case in which the vector is
> an identity and so doesn't need a VEC_PERM_EXPR. I should have realised
> at the time that the other arm of the "if" would need the same fix.
>
> Tested on aarch64-linux-gnu, aarch64_be-elf and x86_64-linux-gnu.
> OK to install?
OK.
Richard.
> Richard
>
>
> 2020-04-22 Richard Sandiford <richard.sandif...@arm.com>
>
> gcc/
> PR tree-optimization/94700
> * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
> an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
> of similarly-structured but distinct vector types.
>
> gcc/testsuite/
> PR tree-optimization/94700
> * gcc.target/aarch64/sve/acle/general/pr94700.c: New test.
> ---
> .../aarch64/sve/acle/general/pr94700.c | 28 +++++++++++++++++++
> gcc/tree-ssa-forwprop.c | 13 ++++++++-
> 2 files changed, 40 insertions(+), 1 deletion(-)
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr94700.c
>
> diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c
> index 1a50045b367..8ee5450b94c 100644
> --- a/gcc/tree-ssa-forwprop.c
> +++ b/gcc/tree-ssa-forwprop.c
> @@ -2475,7 +2475,18 @@ simplify_vector_constructor (gimple_stmt_iterator *gsi)
> orig[0] = gimple_assign_lhs (lowpart);
> }
> if (conv_code == ERROR_MARK)
> - gimple_assign_set_rhs_from_tree (gsi, orig[0]);
> + {
> + tree src_type = TREE_TYPE (orig[0]);
> + if (!useless_type_conversion_p (type, src_type))
> + {
> + gcc_assert (!targetm.compatible_vector_types_p (type,
> src_type));
> + tree rhs = build1 (VIEW_CONVERT_EXPR, type, orig[0]);
> + orig[0] = make_ssa_name (type);
> + gassign *assign = gimple_build_assign (orig[0], rhs);
> + gsi_insert_before (gsi, assign, GSI_SAME_STMT);
> + }
> + gimple_assign_set_rhs_from_tree (gsi, orig[0]);
> + }
> else
> gimple_assign_set_rhs_with_ops (gsi, conv_code, orig[0],
> NULL_TREE, NULL_TREE);
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr94700.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr94700.c
> new file mode 100644
> index 00000000000..1feac60d8e9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr94700.c
> @@ -0,0 +1,28 @@
> +/* { dg-options "-O2 -msve-vector-bits=256" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include <arm_sve.h>
> +
> +typedef float v8sf __attribute__((vector_size(32)));
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +** test:
> +** fadd z0\.s, p0/m, z0\.s, #1.0
> +** fdiv z0\.s, p0/m, z0\.s, z1\.s
> +** ret
> +*/
> +svfloat32_t
> +test (svbool_t pg, svfloat32_t x, svfloat32_t y)
> +{
> + v8sf a = svadd_x (pg, x, 1);
> + v8sf b = { a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7] };
> + return svdiv_x (pg, b, y);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
