[RFC, ARM] Split xorsi with constant after reload

[Richard Henderson]

This follows the other logical patterns, andsi3 and iorsi3, which
also accept reg_or_int_operand and split post-reload.

For the atomic optabs, I have two choices: either rely on this 
post-reload splitting, or call arm_split_constant myself.  Making
all of the logicals work similarly seemed cleaner to me.

Ok?


r~

commit 55a22158e15362bda60bd89b223de9bee72cb52a
Author: Richard Henderson <r...@redhat.com>
Date:   Thu Dec 15 13:34:04 2011 -0800

    arm: Split xorsi with constant after reload.
    
    This puts xorsi3 in the same format as andsi3 and iorsi3.
    This similarity fixes code generation issues with splitting
    atomic_fetch_xor post-reload.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 521d6a3..0e4bc3e 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3049,13 +3049,25 @@
     }"
 )
 
-(define_insn "*arm_xorsi3"
-  [(set (match_operand:SI         0 "s_register_operand" "=r")
-       (xor:SI (match_operand:SI 1 "s_register_operand" "r")
-               (match_operand:SI 2 "arm_rhs_operand" "rI")))]
+(define_insn_and_split "*arm_xorsi3"
+  [(set (match_operand:SI         0 "s_register_operand" "=r,r")
+       (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r")
+               (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))]
   "TARGET_32BIT"
-  "eor%?\\t%0, %1, %2"
-  [(set_attr "predicable" "yes")]
+  "@
+   eor%?\\t%0, %1, %2
+   #"
+  "TARGET_32BIT
+   && GET_CODE (operands[2]) == CONST_INT
+   && !const_ok_for_arm (INTVAL (operands[2]))"
+  [(clobber (const_int 0))]
+{
+  arm_split_constant (XOR, SImode, curr_insn,
+                      INTVAL (operands[2]), operands[0], operands[1], 0);
+  DONE;
+}
+  [(set_attr "length" "4,16")
+   (set_attr "predicable" "yes")]
 )
 
 (define_insn "*thumb1_xorsi3_insn"