These CC_MODEs are identical, merge them into a more generic name.
* config/arm/arm-modes.def (CC_NOTC): New.
(CC_ADC, CC_B): Remove.
* config/arm/arm.c (arm_select_cc_mode): Update to match.
(arm_gen_dicompare_reg): Likewise.
(maybe_get_arm_condition_code): Likewise.
* config/arm/arm.md (uaddvdi4): Likewise.
(addsi3_cin_cout_reg, addsi3_cin_cout_imm): Likewise.
(*addsi3_cin_cout_reg_insn): Likewise.
(*addsi3_cin_cout_imm_insn): Likewise.
(addsi3_cin_cout_0, *addsi3_cin_cout_0_insn): Likewise.
(usubvsi3_borrow, usubvsi3_borrow_imm): Likewise.
---
gcc/config/arm/arm.c | 30 +++++++++++-------------------
gcc/config/arm/arm-modes.def | 12 ++++--------
gcc/config/arm/arm.md | 36 ++++++++++++++++++------------------
gcc/config/arm/iterators.md | 2 +-
gcc/config/arm/predicates.md | 4 ++--
5 files changed, 36 insertions(+), 48 deletions(-)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c38776fdad7..145345c2278 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -15669,7 +15669,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
&& CONST_INT_P (y)
&& UINTVAL (y) == 0x800000000
&& (op == GEU || op == LTU))
- return CC_ADCmode;
+ return CC_NOTCmode;
if (GET_MODE (x) == DImode
&& (op == GE || op == LT)
@@ -15685,7 +15685,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
&& ((GET_CODE (y) == PLUS
&& arm_borrow_operation (XEXP (y, 0), DImode))
|| arm_borrow_operation (y, DImode)))
- return CC_Bmode;
+ return CC_NOTCmode;
if (GET_MODE (x) == DImode
&& (op == EQ || op == NE)
@@ -15879,18 +15879,18 @@ arm_gen_dicompare_reg (rtx_code code, rtx x, rtx y,
rtx scratch)
rtx_insn *insn;
if (y_hi == const0_rtx)
- insn = emit_insn (gen_cmpsi3_0_carryin_CC_Bout (scratch, x_hi,
- cmp1));
+ insn = emit_insn (gen_cmpsi3_0_carryin_CC_NOTCout
+ (scratch, x_hi, cmp1));
else if (CONST_INT_P (y_hi))
{
/* Constant is viewed as unsigned when zero-extended. */
y_hi = GEN_INT (UINTVAL (y_hi) & 0xffffffffULL);
- insn = emit_insn (gen_cmpsi3_imm_carryin_CC_Bout (scratch, x_hi,
- y_hi, cmp1));
+ insn = emit_insn (gen_cmpsi3_imm_carryin_CC_NOTCout
+ (scratch, x_hi, y_hi, cmp1));
}
else
- insn = emit_insn (gen_cmpsi3_carryin_CC_Bout (scratch, x_hi, y_hi,
- cmp1));
+ insn = emit_insn (gen_cmpsi3_carryin_CC_NOTCout
+ (scratch, x_hi, y_hi, cmp1));
return SET_DEST (single_set (insn));
}
@@ -15911,8 +15911,8 @@ arm_gen_dicompare_reg (rtx_code code, rtx x, rtx y, rtx
scratch)
arm_gen_compare_reg (LTU, y_lo, x_lo, scratch),
const0_rtx);
y_hi = GEN_INT (0xffffffff & UINTVAL (y_hi));
- rtx_insn *insn = emit_insn (gen_rscsi3_CC_Bout_scratch (scratch, y_hi,
- x_hi, cmp1));
+ rtx_insn *insn = emit_insn (gen_rscsi3_CC_NOTCout_scratch
+ (scratch, y_hi, x_hi, cmp1));
return SET_DEST (single_set (insn));
}
@@ -24511,7 +24511,7 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
- case E_CC_Bmode:
+ case E_CC_NOTCmode:
switch (comp_code)
{
case GEU: return ARM_CS;
@@ -24527,14 +24527,6 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
- case E_CC_ADCmode:
- switch (comp_code)
- {
- case GEU: return ARM_CS;
- case LTU: return ARM_CC;
- default: return ARM_NV;
- }
-
case E_CCmode:
case E_CC_RSBmode:
switch (comp_code)
diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def
index 6e48223b63d..2495054e066 100644
--- a/gcc/config/arm/arm-modes.def
+++ b/gcc/config/arm/arm-modes.def
@@ -33,18 +33,15 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format ==
ARM_FP16_FORMAT_ALTERNATIVE)
CC_Zmode should be used if only the Z flag is set correctly
CC_Cmode should be used if only the C flag is set correctly, after an
addition.
+ CC_NOTCmode is the inverse of the C flag, after subtraction (borrow),
+ or for ADC where we cannot use the trick of comparing the sum
+ against one of the other operands.
CC_Nmode should be used if only the N (sign) flag is set correctly
CC_NVmode should be used if only the N and V bits are set correctly,
(used for signed comparisons when the carry is propagated in).
CC_RSBmode should be used where the comparison is set by an RSB immediate,
or NEG instruction. The form of the comparison for (const - reg) will
be (COMPARE (not (reg)) (~const)).
- CC_Bmode should be used if only the C flag is correct after a subtract
- (eg after an unsigned borrow with carry-in propagation).
- (used for DImode signed comparisons).
- CC_ADCmode is used when the carry is formed from the output of ADC for an
- addtion. In this case we cannot use the trick of comparing the sum
- against one of the other operands.
CCmode should be used otherwise. */
CC_MODE (CC_NZ);
@@ -65,10 +62,9 @@ CC_MODE (CC_DLTU);
CC_MODE (CC_DGEU);
CC_MODE (CC_DGTU);
CC_MODE (CC_C);
-CC_MODE (CC_B);
+CC_MODE (CC_NOTC);
CC_MODE (CC_N);
CC_MODE (CC_V);
-CC_MODE (CC_ADC);
/* Vector modes. */
VECTOR_MODES (INT, 4); /* V4QI V2HI */
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 7bc55cce61b..90058a1bdb8 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -755,7 +755,7 @@
else
emit_insn (gen_addsi3_cin_cout_reg (hi_result, hi_op1, hi_op2));
- arm_gen_unlikely_cbranch (GEU, CC_ADCmode, operands[3]);
+ arm_gen_unlikely_cbranch (GEU, CC_NOTCmode, operands[3]);
}
DONE;
@@ -764,7 +764,7 @@
(define_expand "addsi3_cin_cout_reg"
[(parallel
[(set (match_dup 3)
- (compare:CC_ADC
+ (compare:CC_NOTC
(plus:DI
(plus:DI (match_dup 4)
(zero_extend:DI (match_operand:SI 1 "s_register_operand")))
@@ -775,7 +775,7 @@
(match_dup 2)))])]
"TARGET_32BIT"
{
- operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
+ operands[3] = gen_rtx_REG (CC_NOTCmode, CC_REGNUM);
rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
@@ -783,8 +783,8 @@
)
(define_insn "*addsi3_cin_cout_reg_insn"
- [(set (reg:CC_ADC CC_REGNUM)
- (compare:CC_ADC
+ [(set (reg:CC_NOTC CC_REGNUM)
+ (compare:CC_NOTC
(plus:DI
(plus:DI
(match_operand:DI 3 "arm_carry_operation" "")
@@ -807,7 +807,7 @@
(define_expand "addsi3_cin_cout_imm"
[(parallel
[(set (match_dup 3)
- (compare:CC_ADC
+ (compare:CC_NOTC
(plus:DI
(plus:DI (match_dup 4)
(zero_extend:DI (match_operand:SI 1 "s_register_operand")))
@@ -818,7 +818,7 @@
(match_operand:SI 2 "arm_adcimm_operand")))])]
"TARGET_32BIT"
{
- operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
+ operands[3] = gen_rtx_REG (CC_NOTCmode, CC_REGNUM);
rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
@@ -827,8 +827,8 @@
)
(define_insn "*addsi3_cin_cout_imm_insn"
- [(set (reg:CC_ADC CC_REGNUM)
- (compare:CC_ADC
+ [(set (reg:CC_NOTC CC_REGNUM)
+ (compare:CC_NOTC
(plus:DI
(plus:DI
(match_operand:DI 3 "arm_carry_operation" "")
@@ -850,7 +850,7 @@
(define_expand "addsi3_cin_cout_0"
[(parallel
[(set (match_dup 2)
- (compare:CC_ADC
+ (compare:CC_NOTC
(plus:DI (match_dup 3)
(zero_extend:DI (match_operand:SI 1 "s_register_operand")))
(const_int 4294967296)))
@@ -858,7 +858,7 @@
(plus:SI (match_dup 4) (match_dup 1)))])]
"TARGET_32BIT"
{
- operands[2] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
+ operands[2] = gen_rtx_REG (CC_NOTCmode, CC_REGNUM);
rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
operands[3] = gen_rtx_LTU (DImode, ccin, const0_rtx);
operands[4] = gen_rtx_LTU (SImode, ccin, const0_rtx);
@@ -866,8 +866,8 @@
)
(define_insn "*addsi3_cin_cout_0_insn"
- [(set (reg:CC_ADC CC_REGNUM)
- (compare:CC_ADC
+ [(set (reg:CC_NOTC CC_REGNUM)
+ (compare:CC_NOTC
(plus:DI
(match_operand:DI 2 "arm_carry_operation" "")
(zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))
@@ -1616,7 +1616,7 @@
emit_insn (gen_usubvsi3_borrow (hi_result, hi_op1, hi_op2,
gen_rtx_LTU (SImode, ccreg, const0_rtx),
gen_rtx_LTU (DImode, ccreg, const0_rtx)));
- arm_gen_unlikely_cbranch (LTU, CC_Bmode, operands[3]);
+ arm_gen_unlikely_cbranch (LTU, CC_NOTCmode, operands[3]);
DONE;
})
@@ -2109,8 +2109,8 @@
)
(define_insn "usubvsi3_borrow"
- [(set (reg:CC_B CC_REGNUM)
- (compare:CC_B
+ [(set (reg:CC_NOTC CC_REGNUM)
+ (compare:CC_NOTC
(zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r"))
(plus:DI (match_operand:DI 4 "arm_borrow_operation" "")
(zero_extend:DI
@@ -2127,8 +2127,8 @@
)
(define_insn "usubvsi3_borrow_imm"
- [(set (reg:CC_B CC_REGNUM)
- (compare:CC_B
+ [(set (reg:CC_NOTC CC_REGNUM)
+ (compare:CC_NOTC
(zero_extend:DI (match_operand:SI 1 "s_register_operand" "r,r"))
(plus:DI (match_operand:DI 5 "arm_borrow_operation" "")
(match_operand:DI 3 "const_int_operand" "n,n"))))
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 0bc9eba0722..54539d1edf9 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -907,7 +907,7 @@
;; Determine the mode of a 'wide compare', ie where the carry flag is
;; propagated into the comparison.
-(define_code_attr CC_EXTEND [(sign_extend "CC_NV") (zero_extend "CC_B")])
+(define_code_attr CC_EXTEND [(sign_extend "CC_NV") (zero_extend "CC_NOTC")])
;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 009862e012c..abd0b5c2c55 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -478,7 +478,7 @@
machine_mode ccmode = GET_MODE (op0);
if (ccmode == CC_Cmode)
return GET_CODE (op) == LTU;
- else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode)
+ else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_NOTCmode)
return GET_CODE (op) == GEU;
return false;
@@ -500,7 +500,7 @@
machine_mode ccmode = GET_MODE (op0);
if (ccmode == CC_Cmode)
return GET_CODE (op) == GEU;
- else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode)
+ else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_NOTCmode)
return GET_CODE (op) == LTU;
return false;
}
--
2.20.1
