On Tue, Mar 31, 2020 at 2:07 AM Kito Cheng <kito.ch...@sifive.com> wrote: > - Implied rule are introduced into latest RISC-V isa spec. > > - Only implemented D implied F-extension. Zicsr and Zifence are not > implement yet, so the rule not included in this patch.
When I try this patch, I see an error: rohan:2132$ ./xgcc -B./ -O -march=rv64imafdc -mabi=lp64d tmp.c /tmp/ccULN36f.s: Assembler messages: /tmp/ccULN36f.s:3: Fatal error: -march=rv64i2p0_m2p0_a2p0_f2p0_f2p0_d2p0_c2p0: ISA string is not in canonical order. `f' rohan:2133$ Looks like you need to make sure that we don't add the implied F if it is already there. Otherwise, this looks OK to me. We don't have support for these implied extensions in binutils yet. If we are adding it to gcc, we should probably add it to binutils too. Maybe you can ask Nelson to work on that. > + /* TODO: Implied extension might use differet version. */ differet -> different Jim
