On Fri, Apr 3, 2020 at 7:30 PM Jakub Jelinek <ja...@redhat.com> wrote:
>
> Hi!
>
> In https://gcc.gnu.org/ml/gcc-patches/2017-10/msg00576.html the builtin
> handling was changed so that OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE
> etc. in i386-builtin.def means we require both mmx and sse, not just one of
> those, and later on for other option combinations very similar rule has
> been clarified, with a few exceptions that ix86_expand_builtin lists
> (SSE | 3DNOW_A, SSE4_2 | CRC32 and FMA | FMA4 are one or the other).
> The above mentioned patch also added OPTION_MASK_ISA_MMX to a few insns
> that in the ISA documents are documented e.g. only requiring SSE2 or SSSE3
> etc. CPUID, but because those builtins take or return V2SI or similar
> MMX-ish arguments, we can't really support those builtins in functions that
> have MMX disabled.
> Now, during the TARGET_MMX_WITH_SSE changes,
> https://gcc.gnu.org/ml/gcc-patches/2019-02/msg01479.html
> and
> https://gcc.gnu.org/ml/gcc-patches/2019-05/msg01084.html
> actually changed this; it added | OPTION_MASK_ISA_SSE2 to builtins
> that were formerly OPTION_MASK_ISA_MMX only, but didn't touch the builtins
> that were already using OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX
> for something different (both options must be enabled).
> This causes e.g. ICE on the following testcase, because the builtins are
> now enabled even with just -mmmx -mno-sse2, even when they (those changed in
> 2017) require SSE2.
> The following patch instead reverts the above two 2019-ish changes (except
> for header/testsuite changes), and instead treats OPTION_MASK_ISA_MMX
> requirement in bdesc/.isa specially, as being satisfied by either
> TARGET_MMX (no changes really needed for that), or by TARGET_MMX_WITH_SSE.
> This achieves what the two 2019-ish patches want to do, that the
> OPTION_MASK_ISA_MMX only builtins are enabled not just with -mmmx, but also
> with -m64 -msse2, and for the other builtins that require MMX and something
> else will either require -mmmx and that some other ISA, or -m64 -msse2 and
> that other ISA, but -mmmx will not enable builtins that need something more
> than OPTION_MASK_ISA_MMX only.
> The i386-builtins.c changes that aren't reversion of the two patches try to
> make sure that in .isa we still record OPTION_MASK_ISA_MMX for builtins that
> have that requirement, so that it is in the end only ix86_expand_builtin
> that decides if the builtin is ok or not and the rest of code just decides
> if it is the right time to declare the builtin already or if it should be
> deferred.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2020-04-03 Jakub Jelinek <ja...@redhat.com>
>
> PR target/94461
> * config/i386/i386-expand.c (ix86_expand_builtin): If
> TARGET_MMX_WITH_SSE without TARGET_MMX and bisa contains
> OPTION_MASK_ISA_MMX, clear OPTION_MASK_ISA_MMX and set
> OPTION_MASK_ISA_SSE2 in bisa. Revert 2019-05-17 and 2019-05-15
> changes.
> * config/i386/i386-builtins.c (def_builtin): If mask includes
> OPTION_MASK_ISA_MMX and TARGET_MMX_WITH_SSE, consider it satisfied.
> (ix86_add_new_builtins): For TARGET_64BIT, consider
> OPTION_MASK_ISA_SSE2 enabled in isa as satisfying OPTION_MASK_ISA_MMX
> requirement.
> (ix86_init_tm_builtins): If TARGET_MMX_WITH_SSE consider
> OPTION_MASK_ISA_MMX as satisfied.
> (bdesc_tm): Revert 2019-05-15 changes.
> (ix86_init_mmx_sse_builtins): Likewise.
> * config/i386/i386-builtin.def: Likewise.
>
> * gcc.target/i386/pr94461.c: New test.
LGTM (following the logic through the code literally gave me a
headache) since you know .isa recording stuff better than I.
Please note the comment in the testcase.
Thanks,
Uros.
> --- gcc/config/i386/i386-expand.c.jj 2020-04-03 15:41:29.246722608 +0200
> +++ gcc/config/i386/i386-expand.c 2020-04-03 15:42:17.588002941 +0200
> @@ -10968,8 +10968,9 @@ ix86_expand_builtin (tree exp, rtx targe
> OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A
> OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32
> OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4
> - where for each this pair it is sufficient if either of the ISAs is
> - enabled, plus if it is ored with other options also those others. */
> + where for each such pair it is sufficient if either of the ISAs is
> + enabled, plus if it is ored with other options also those others.
> + OPTION_MASK_ISA_MMX in bisa is satisfied also if TARGET_MMX_WITH_SSE.
> */
> if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A))
> == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A))
> && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A)) != 0)
> @@ -10982,24 +10983,10 @@ ix86_expand_builtin (tree exp, rtx targe
> == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
> && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
> isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
> - /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when
> - MMX is disabled. NB: Since MMX intrinsics are marked with
> - SSE/SSE2/SSSE3, enable them without SSE/SSE2/SSSE3 if MMX is
> - enabled. */
> - if (TARGET_MMX || TARGET_MMX_WITH_SSE)
> + if ((bisa & OPTION_MASK_ISA_MMX) && !TARGET_MMX && TARGET_MMX_WITH_SSE)
> {
> - if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
> - == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX))
> - && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) != 0)
> - isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX);
> - if (((bisa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
> - == (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX))
> - && (isa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) != 0)
> - isa |= (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX);
> - if (((bisa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
> - == (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX))
> - && (isa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) != 0)
> - isa |= (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX);
> + bisa &= ~OPTION_MASK_ISA_MMX;
> + bisa |= OPTION_MASK_ISA_SSE2;
> }
> if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
> {
> --- gcc/config/i386/i386-builtins.c.jj 2020-04-03 15:41:29.244722638 +0200
> +++ gcc/config/i386/i386-builtins.c 2020-04-03 15:42:17.591002896 +0200
> @@ -274,6 +274,7 @@ def_builtin (HOST_WIDE_INT mask, HOST_WI
>
> if (((mask2 == 0 || (mask2 & ix86_isa_flags2) != 0)
> && (mask == 0 || (mask & ix86_isa_flags) != 0))
> + || ((mask & OPTION_MASK_ISA_MMX) != 0 && TARGET_MMX_WITH_SSE)
> || (lang_hooks.builtin_function
> == lang_hooks.builtin_function_ext_scope))
> {
> @@ -341,12 +342,16 @@ ix86_add_new_builtins (HOST_WIDE_INT isa
> isa &= ~OPTION_MASK_ISA_64BIT;
>
> if ((isa & deferred_isa_values) == 0
> - && (isa2 & deferred_isa_values2) == 0)
> + && (isa2 & deferred_isa_values2) == 0
> + && ((deferred_isa_values & OPTION_MASK_ISA_MMX) == 0
> + || !(TARGET_64BIT && (isa & OPTION_MASK_ISA_SSE2) != 0)))
> return;
>
> /* Bits in ISA value can be removed from potential isa values. */
> deferred_isa_values &= ~isa;
> deferred_isa_values2 &= ~isa2;
> + if (TARGET_64BIT && (isa & OPTION_MASK_ISA_SSE2) != 0)
> + deferred_isa_values &= ~OPTION_MASK_ISA_MMX;
>
> int i;
> tree saved_current_target_pragma = current_target_pragma;
> @@ -355,7 +360,10 @@ ix86_add_new_builtins (HOST_WIDE_INT isa
> for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
> {
> if (((ix86_builtins_isa[i].isa & isa) != 0
> - || (ix86_builtins_isa[i].isa2 & isa2) != 0)
> + || (ix86_builtins_isa[i].isa2 & isa2) != 0
> + || ((ix86_builtins_isa[i].isa & OPTION_MASK_ISA_MMX) != 0
> + && TARGET_64BIT
> + && (isa & OPTION_MASK_ISA_SSE2) != 0))
> && ix86_builtins_isa[i].set_and_not_built_p)
> {
> tree decl, type;
> @@ -383,13 +391,13 @@ ix86_add_new_builtins (HOST_WIDE_INT isa
> we're lazy. Add casts to make them fit. */
> static const struct builtin_description bdesc_tm[] =
> {
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN,
> VOID_FTYPE_PV2SI_V2SI },
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64,
> UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64,
> UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN,
> V2SI_FTYPE_PCV2SI },
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64,
> UNKNOWN, V2SI_FTYPE_PCV2SI },
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64,
> UNKNOWN, V2SI_FTYPE_PCV2SI },
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64,
> UNKNOWN, V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum
> ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum
> ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum
> ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum
> ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
>
> { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum
> ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
> { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM128",
> (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN,
> VOID_FTYPE_PV4SF_V4SF },
> @@ -407,7 +415,7 @@ static const struct builtin_description
> { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM256",
> (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
> { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM256",
> (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
>
> - { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing,
> "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN,
> VOID_FTYPE_PCVOID },
> + { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum
> ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
> { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum
> ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
> { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum
> ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
> };
> @@ -450,6 +458,7 @@ ix86_init_tm_builtins (void)
> i++, d++)
> {
> if ((d->mask & ix86_isa_flags) != 0
> + || ((d->mask & OPTION_MASK_ISA_MMX) != 0 && TARGET_MMX_WITH_SSE)
> || (lang_hooks.builtin_function
> == lang_hooks.builtin_function_ext_scope))
> {
> @@ -1057,16 +1066,16 @@ ix86_init_mmx_sse_builtins (void)
> VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT);
>
> /* MMX access to the vec_init patterns. */
> - def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + def_builtin_const (OPTION_MASK_ISA_MMX, 0,
> "__builtin_ia32_vec_init_v2si",
> V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
>
> - def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + def_builtin_const (OPTION_MASK_ISA_MMX, 0,
> "__builtin_ia32_vec_init_v4hi",
> V4HI_FTYPE_HI_HI_HI_HI,
> IX86_BUILTIN_VEC_INIT_V4HI);
>
> - def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + def_builtin_const (OPTION_MASK_ISA_MMX, 0,
> "__builtin_ia32_vec_init_v8qi",
> V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
> IX86_BUILTIN_VEC_INIT_V8QI);
> @@ -1089,7 +1098,7 @@ ix86_init_mmx_sse_builtins (void)
> "__builtin_ia32_vec_ext_v4hi",
> HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);
>
> - def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> + def_builtin_const (OPTION_MASK_ISA_MMX, 0,
> "__builtin_ia32_vec_ext_v2si",
> SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI);
>
> --- gcc/config/i386/i386-builtin.def.jj 2020-04-03 15:41:29.244722638 +0200
> +++ gcc/config/i386/i386-builtin.def 2020-04-03 15:42:17.592002881 +0200
> @@ -100,7 +100,7 @@ BDESC (0, 0, CODE_FOR_fnstsw, "__builtin
> BDESC (0, 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX,
> UNKNOWN, (int) VOID_FTYPE_VOID)
>
> /* MMX */
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_emms,
> "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms",
> IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
>
> /* 3DNow! */
> BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_femms, "__builtin_ia32_femms",
> IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID)
> @@ -458,68 +458,68 @@ BDESC (0, 0, CODE_FOR_rotrqi3, "__builti
> BDESC (0, 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI,
> UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)
>
> /* MMX */
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv8qi3,
> "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv4hi3,
> "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv2si3,
> "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv8qi3,
> "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv4hi3,
> "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv2si3,
> "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_mulv4hi3,
> "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw",
> IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andv2si3,
> "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_iorv2si3,
> "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_xorv2si3,
> "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv8qi3,
> "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv4hi3,
> "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv2si3,
> "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv8qi3,
> "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv4hi3,
> "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv2si3,
> "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW,
> UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packsswb,
> "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packssdw,
> "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int)
> V4HI_FTYPE_V2SI_V2SI)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packuswb,
> "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_pmaddwd,
> "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int)
> V2SI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI,
> UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN,
> (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN,
> (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN,
> (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI,
> UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN,
> (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN,
> (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN,
> (int) V1DI_FTYPE_V1DI_V1DI_COUNT)
> -
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI,
> UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI,
> UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN,
> (int) V4HI_FTYPE_V4HI_V4HI_COUNT)
> -BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0,
> CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN,
> (int) V2SI_FTYPE_V2SI_V2SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv8qi3,
> "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv4hi3,
> "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv2si3,
> "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv8qi3,
> "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv4hi3,
> "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv2si3,
> "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv8qi3,
> "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv4hi3,
> "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv8qi3,
> "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv4hi3,
> "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv8qi3,
> "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv4hi3,
> "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv8qi3,
> "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv4hi3,
> "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_mulv4hi3,
> "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_smulv4hi3_highpart,
> "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand",
> IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andnotv2si3,
> "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por",
> IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor",
> IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv8qi3,
> "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv4hi3,
> "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv2si3,
> "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv8qi3,
> "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv4hi3,
> "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv2si3,
> "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhbw,
> "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhwd,
> "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhdq,
> "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklbw,
> "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int)
> V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklwd,
> "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckldq,
> "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packsswb,
> "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packssdw,
> "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int)
> V4HI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packuswb,
> "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int)
> V8QI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_pmaddwd,
> "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int)
> V2SI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3,
> "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3,
> "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3,
> "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3,
> "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3,
> "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3,
> "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_V1DI_COUNT)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3,
> "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3,
> "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3,
> "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3,
> "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3,
> "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3,
> "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int)
> V1DI_FTYPE_V1DI_V1DI_COUNT)
> +
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3,
> "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3,
> "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_SI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3,
> "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int)
> V4HI_FTYPE_V4HI_V4HI_COUNT)
> +BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3,
> "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int)
> V2SI_FTYPE_V2SI_V2SI_COUNT)
>
> /* 3DNow! */
> BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id",
> IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF)
> --- gcc/testsuite/gcc.target/i386/pr94461.c.jj 2020-04-03 15:53:03.816385710
> +0200
> +++ gcc/testsuite/gcc.target/i386/pr94461.c 2020-04-03 15:52:34.600820434
> +0200
> @@ -0,0 +1,11 @@
> +/* PR target/94461 */
> +/* { dg-do compile { target lp64 } } */
There is no need for the target selector, the testcase also fails with
-m32 for me. Maybe you need to add -msse option to avoid "SSE register
return with SSE disabled" error?
> +/* { dg-options "-mmmx -mno-sse2" } */
> +
> +typedef int __v2si __attribute__ ((__vector_size__ (8)));
> +
> +__v2si
> +foo (__v2si a)
> +{
> + return (__v2si) __builtin_ia32_pmuludq (a, a); /* { dg-error "needs
> isa option" } */
> +}
>
> Jakub
>
