Hi!
On Thu, Mar 26, 2020 at 05:06:43AM -0500, luo...@linux.ibm.com wrote:
> Remove split code from add<mode>3 to allow a later pass to split.
> This allows later logic to hoist out constant load in add instructions.
> In loop, lis+ori could be hoisted out to improve performance compared with
> previous addis+addi (About 15% on typical case), weak point is
> one more register is used and one more instruction is generated. i.e.:
>
> addis 3,3,0x8765
> addi 3,3,0x4321
>
> =>
>
> lis 9,0x8765
> ori 9,9,0x4321
> add 3,3,9
What does it do overall? Say, to SPEC. What does it do to execution
time, and what does it do to binary size?
Do we want something later in the RTL pipeline to make "addi"s etc. again?
> 2020-03-26 Xiong Hu Luo <luo...@linux.ibm.com>
>
> * config/rs6000/rs6000.md (add<mode>3): Remove split code, move constant
> to temp register before add.
This should not be indented, so just:
* config/rs6000/rs6000.md (add<mode>3): Remove split code, move constant
to temp register before add.
We have six separate add<mode>3 patterns (three of those are in rs6000.md,
too). You can write something like
(add<mode>3 for SDI):
to show which iterator (or mode) this one is for. This is helpful with
any <mode> or <code> or the like, even if there (currently) is only one
pattern you could mean.
> diff --git a/gcc/testsuite/gcc.target/powerpc/add-const.c
> b/gcc/testsuite/gcc.target/powerpc/add-const.c
> new file mode 100644
> index 00000000000..e1007247b32
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/add-const.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile { target { lp64 } } } */
> +/* { dg-options "-O3 -fno-unroll-loops" } */
> +
> +/* Ensure the lis,ori are generated, which indicates they have
> + been hoisted outside of the loop. */
This sounds a bit fragile -- but we'll see :-) It is small code, so it
probably will be fine, it won't change its generated code often.
Segher
