Hi Srinath, > -----Original Message----- > From: Srinath Parvathaneni <srinath.parvathan...@arm.com> > Sent: 18 March 2020 11:32 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com> > Subject: [PATCH v2][ARM][GCC][3/4x]: MVE intrinsics with quaternary > operands. > > Hello Kyrill, > > Following patch is the rebased version of v1. > (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019- > November/534324.html > > #### > Hello, > > This patch supports following MVE ACLE intrinsics with quaternary operands. > > vmlaldavaq_p_s16, vmlaldavaq_p_s32, vmlaldavaq_p_u16, > vmlaldavaq_p_u32, vmlaldavaxq_p_s16, vmlaldavaxq_p_s32, > vmlaldavaxq_p_u16, vmlaldavaxq_p_u32, vmlsldavaq_p_s16, > vmlsldavaq_p_s32, vmlsldavaxq_p_s16, vmlsldavaxq_p_s32, > vmullbq_poly_m_p16, vmullbq_poly_m_p8, vmulltq_poly_m_p16, > vmulltq_poly_m_p8, vqdmullbq_m_n_s16, vqdmullbq_m_n_s32, > vqdmullbq_m_s16, vqdmullbq_m_s32, vqdmulltq_m_n_s16, > vqdmulltq_m_n_s32, vqdmulltq_m_s16, vqdmulltq_m_s32, > vqrshrnbq_m_n_s16, vqrshrnbq_m_n_s32, vqrshrnbq_m_n_u16, > vqrshrnbq_m_n_u32, vqrshrntq_m_n_s16, vqrshrntq_m_n_s32, > vqrshrntq_m_n_u16, vqrshrntq_m_n_u32, vqrshrunbq_m_n_s16, > vqrshrunbq_m_n_s32, vqrshruntq_m_n_s16, vqrshruntq_m_n_s32, > vqshrnbq_m_n_s16, vqshrnbq_m_n_s32, vqshrnbq_m_n_u16, > vqshrnbq_m_n_u32, vqshrntq_m_n_s16, vqshrntq_m_n_s32, > vqshrntq_m_n_u16, vqshrntq_m_n_u32, vqshrunbq_m_n_s16, > vqshrunbq_m_n_s32, vqshruntq_m_n_s16, vqshruntq_m_n_s32, > vrmlaldavhaq_p_s32, vrmlaldavhaq_p_u32, vrmlaldavhaxq_p_s32, > vrmlsldavhaq_p_s32, vrmlsldavhaxq_p_s32, vrshrnbq_m_n_s16, > vrshrnbq_m_n_s32, vrshrnbq_m_n_u16, vrshrnbq_m_n_u32, > vrshrntq_m_n_s16, vrshrntq_m_n_s32, vrshrntq_m_n_u16, > vrshrntq_m_n_u32, vshllbq_m_n_s16, vshllbq_m_n_s8, vshllbq_m_n_u16, > vshllbq_m_n_u8, vshlltq_m_n_s16, vshlltq_m_n_s8, vshlltq_m_n_u16, > vshlltq_m_n_u8, vshrnbq_m_n_s16, vshrnbq_m_n_s32, vshrnbq_m_n_u16, > vshrnbq_m_n_u32, vshrntq_m_n_s16, vshrntq_m_n_s32, vshrntq_m_n_u16, > vshrntq_m_n_u32. > > Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more > details. > [1] https://developer.arm.com/architectures/instruction-sets/simd- > isas/helium/mve-intrinsics > > Regression tested on arm-none-eabi and found no regressions. > > Ok for trunk?
Thanks, I've pushed this patch to master. Kyrill > > Thanks, > Srinath. > > gcc/ChangeLog: > > 2019-10-31 Andre Vieira <andre.simoesdiasvie...@arm.com> > Mihail Ionescu <mihail.ione...@arm.com> > Srinath Parvathaneni <srinath.parvathan...@arm.com> > > * config/arm/arm-protos.h (arm_mve_immediate_check): > * config/arm/arm.c (arm_mve_immediate_check): Define fuction to > check > mode and interger value. > * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro. > (vmlaldavaq_p_s16): Likewise. > (vmlaldavaq_p_u32): Likewise. > (vmlaldavaq_p_u16): Likewise. > (vmlaldavaxq_p_s32): Likewise. > (vmlaldavaxq_p_s16): Likewise. > (vmlaldavaxq_p_u32): Likewise. > (vmlaldavaxq_p_u16): Likewise. > (vmlsldavaq_p_s32): Likewise. > (vmlsldavaq_p_s16): Likewise. > (vmlsldavaxq_p_s32): Likewise. > (vmlsldavaxq_p_s16): Likewise. > (vmullbq_poly_m_p8): Likewise. > (vmullbq_poly_m_p16): Likewise. > (vmulltq_poly_m_p8): Likewise. > (vmulltq_poly_m_p16): Likewise. > (vqdmullbq_m_n_s32): Likewise. > (vqdmullbq_m_n_s16): Likewise. > (vqdmullbq_m_s32): Likewise. > (vqdmullbq_m_s16): Likewise. > (vqdmulltq_m_n_s32): Likewise. > (vqdmulltq_m_n_s16): Likewise. > (vqdmulltq_m_s32): Likewise. > (vqdmulltq_m_s16): Likewise. > (vqrshrnbq_m_n_s32): Likewise. > (vqrshrnbq_m_n_s16): Likewise. > (vqrshrnbq_m_n_u32): Likewise. > (vqrshrnbq_m_n_u16): Likewise. > (vqrshrntq_m_n_s32): Likewise. > (vqrshrntq_m_n_s16): Likewise. > (vqrshrntq_m_n_u32): Likewise. > (vqrshrntq_m_n_u16): Likewise. > (vqrshrunbq_m_n_s32): Likewise. > (vqrshrunbq_m_n_s16): Likewise. > (vqrshruntq_m_n_s32): Likewise. > (vqrshruntq_m_n_s16): Likewise. > (vqshrnbq_m_n_s32): Likewise. > (vqshrnbq_m_n_s16): Likewise. > (vqshrnbq_m_n_u32): Likewise. > (vqshrnbq_m_n_u16): Likewise. > (vqshrntq_m_n_s32): Likewise. > (vqshrntq_m_n_s16): Likewise. > (vqshrntq_m_n_u32): Likewise. > (vqshrntq_m_n_u16): Likewise. > (vqshrunbq_m_n_s32): Likewise. > (vqshrunbq_m_n_s16): Likewise. > (vqshruntq_m_n_s32): Likewise. > (vqshruntq_m_n_s16): Likewise. > (vrmlaldavhaq_p_s32): Likewise. > (vrmlaldavhaq_p_u32): Likewise. > (vrmlaldavhaxq_p_s32): Likewise. > (vrmlsldavhaq_p_s32): Likewise. > (vrmlsldavhaxq_p_s32): Likewise. > (vrshrnbq_m_n_s32): Likewise. > (vrshrnbq_m_n_s16): Likewise. > (vrshrnbq_m_n_u32): Likewise. > (vrshrnbq_m_n_u16): Likewise. > (vrshrntq_m_n_s32): Likewise. > (vrshrntq_m_n_s16): Likewise. > (vrshrntq_m_n_u32): Likewise. > (vrshrntq_m_n_u16): Likewise. > (vshllbq_m_n_s8): Likewise. > (vshllbq_m_n_s16): Likewise. > (vshllbq_m_n_u8): Likewise. > (vshllbq_m_n_u16): Likewise. > (vshlltq_m_n_s8): Likewise. > (vshlltq_m_n_s16): Likewise. > (vshlltq_m_n_u8): Likewise. > (vshlltq_m_n_u16): Likewise. > (vshrnbq_m_n_s32): Likewise. > (vshrnbq_m_n_s16): Likewise. > (vshrnbq_m_n_u32): Likewise. > (vshrnbq_m_n_u16): Likewise. > (vshrntq_m_n_s32): Likewise. > (vshrntq_m_n_s16): Likewise. > (vshrntq_m_n_u32): Likewise. > (vshrntq_m_n_u16): Likewise. > (__arm_vmlaldavaq_p_s32): Define intrinsic. > (__arm_vmlaldavaq_p_s16): Likewise. > (__arm_vmlaldavaq_p_u32): Likewise. > (__arm_vmlaldavaq_p_u16): Likewise. > (__arm_vmlaldavaxq_p_s32): Likewise. > (__arm_vmlaldavaxq_p_s16): Likewise. > (__arm_vmlaldavaxq_p_u32): Likewise. > (__arm_vmlaldavaxq_p_u16): Likewise. > (__arm_vmlsldavaq_p_s32): Likewise. > (__arm_vmlsldavaq_p_s16): Likewise. > (__arm_vmlsldavaxq_p_s32): Likewise. > (__arm_vmlsldavaxq_p_s16): Likewise. > (__arm_vmullbq_poly_m_p8): Likewise. > (__arm_vmullbq_poly_m_p16): Likewise. > (__arm_vmulltq_poly_m_p8): Likewise. > (__arm_vmulltq_poly_m_p16): Likewise. > (__arm_vqdmullbq_m_n_s32): Likewise. > (__arm_vqdmullbq_m_n_s16): Likewise. > (__arm_vqdmullbq_m_s32): Likewise. > (__arm_vqdmullbq_m_s16): Likewise. > (__arm_vqdmulltq_m_n_s32): Likewise. > (__arm_vqdmulltq_m_n_s16): Likewise. > (__arm_vqdmulltq_m_s32): Likewise. > (__arm_vqdmulltq_m_s16): Likewise. > (__arm_vqrshrnbq_m_n_s32): Likewise. > (__arm_vqrshrnbq_m_n_s16): Likewise. > (__arm_vqrshrnbq_m_n_u32): Likewise. > (__arm_vqrshrnbq_m_n_u16): Likewise. > (__arm_vqrshrntq_m_n_s32): Likewise. > (__arm_vqrshrntq_m_n_s16): Likewise. > (__arm_vqrshrntq_m_n_u32): Likewise. > (__arm_vqrshrntq_m_n_u16): Likewise. > (__arm_vqrshrunbq_m_n_s32): Likewise. > (__arm_vqrshrunbq_m_n_s16): Likewise. > (__arm_vqrshruntq_m_n_s32): Likewise. > (__arm_vqrshruntq_m_n_s16): Likewise. > (__arm_vqshrnbq_m_n_s32): Likewise. > (__arm_vqshrnbq_m_n_s16): Likewise. > (__arm_vqshrnbq_m_n_u32): Likewise. > (__arm_vqshrnbq_m_n_u16): Likewise. > (__arm_vqshrntq_m_n_s32): Likewise. > (__arm_vqshrntq_m_n_s16): Likewise. > (__arm_vqshrntq_m_n_u32): Likewise. > (__arm_vqshrntq_m_n_u16): Likewise. > (__arm_vqshrunbq_m_n_s32): Likewise. > (__arm_vqshrunbq_m_n_s16): Likewise. > (__arm_vqshruntq_m_n_s32): Likewise. > (__arm_vqshruntq_m_n_s16): Likewise. > (__arm_vrmlaldavhaq_p_s32): Likewise. > (__arm_vrmlaldavhaq_p_u32): Likewise. > (__arm_vrmlaldavhaxq_p_s32): Likewise. > (__arm_vrmlsldavhaq_p_s32): Likewise. > (__arm_vrmlsldavhaxq_p_s32): Likewise. > (__arm_vrshrnbq_m_n_s32): Likewise. > (__arm_vrshrnbq_m_n_s16): Likewise. > (__arm_vrshrnbq_m_n_u32): Likewise. > (__arm_vrshrnbq_m_n_u16): Likewise. > (__arm_vrshrntq_m_n_s32): Likewise. > (__arm_vrshrntq_m_n_s16): Likewise. > (__arm_vrshrntq_m_n_u32): Likewise. > (__arm_vrshrntq_m_n_u16): Likewise. > (__arm_vshllbq_m_n_s8): Likewise. > (__arm_vshllbq_m_n_s16): Likewise. > (__arm_vshllbq_m_n_u8): Likewise. > (__arm_vshllbq_m_n_u16): Likewise. > (__arm_vshlltq_m_n_s8): Likewise. > (__arm_vshlltq_m_n_s16): Likewise. > (__arm_vshlltq_m_n_u8): Likewise. > (__arm_vshlltq_m_n_u16): Likewise. > (__arm_vshrnbq_m_n_s32): Likewise. > (__arm_vshrnbq_m_n_s16): Likewise. > (__arm_vshrnbq_m_n_u32): Likewise. > (__arm_vshrnbq_m_n_u16): Likewise. > (__arm_vshrntq_m_n_s32): Likewise. > (__arm_vshrntq_m_n_s16): Likewise. > (__arm_vshrntq_m_n_u32): Likewise. > (__arm_vshrntq_m_n_u16): Likewise. > (vmullbq_poly_m): Define polymorphic variant. > (vmulltq_poly_m): Likewise. > (vshllbq_m): Likewise. > (vshrntq_m_n): Likewise. > (vshrnbq_m_n): Likewise. > (vshlltq_m_n): Likewise. > (vshllbq_m_n): Likewise. > (vrshrntq_m_n): Likewise. > (vrshrnbq_m_n): Likewise. > (vqshruntq_m_n): Likewise. > (vqshrunbq_m_n): Likewise. > (vqdmullbq_m_n): Likewise. > (vqdmullbq_m): Likewise. > (vqdmulltq_m_n): Likewise. > (vqdmulltq_m): Likewise. > (vqrshrnbq_m_n): Likewise. > (vqrshrntq_m_n): Likewise. > (vqrshrunbq_m_n): Likewise. > (vqrshruntq_m_n): Likewise. > (vqshrnbq_m_n): Likewise. > (vqshrntq_m_n): Likewise. > * config/arm/arm_mve_builtins.def > (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use > builtin qualifiers. > (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. > (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. > (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. > (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. > * config/arm/mve.md (VMLALDAVAQ_P): Define iterator. > (VMLALDAVAXQ_P): Likewise. > (VQRSHRNBQ_M_N): Likewise. > (VQRSHRNTQ_M_N): Likewise. > (VQSHRNBQ_M_N): Likewise. > (VQSHRNTQ_M_N): Likewise. > (VRSHRNBQ_M_N): Likewise. > (VRSHRNTQ_M_N): Likewise. > (VSHLLBQ_M_N): Likewise. > (VSHLLTQ_M_N): Likewise. > (VSHRNBQ_M_N): Likewise. > (VSHRNTQ_M_N): Likewise. > (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern. > (mve_vmlaldavaxq_p_<supf><mode>): Likewise. > (mve_vqrshrnbq_m_n_<supf><mode>): Likewise. > (mve_vqrshrntq_m_n_<supf><mode>): Likewise. > (mve_vqshrnbq_m_n_<supf><mode>): Likewise. > (mve_vqshrntq_m_n_<supf><mode>): Likewise. > (mve_vrmlaldavhaq_p_sv4si): Likewise. > (mve_vrshrnbq_m_n_<supf><mode>): Likewise. > (mve_vrshrntq_m_n_<supf><mode>): Likewise. > (mve_vshllbq_m_n_<supf><mode>): Likewise. > (mve_vshlltq_m_n_<supf><mode>): Likewise. > (mve_vshrnbq_m_n_<supf><mode>): Likewise. > (mve_vshrntq_m_n_<supf><mode>): Likewise. > (mve_vmlsldavaq_p_s<mode>): Likewise. > (mve_vmlsldavaxq_p_s<mode>): Likewise. > (mve_vmullbq_poly_m_p<mode>): Likewise. > (mve_vmulltq_poly_m_p<mode>): Likewise. > (mve_vqdmullbq_m_n_s<mode>): Likewise. > (mve_vqdmullbq_m_s<mode>): Likewise. > (mve_vqdmulltq_m_n_s<mode>): Likewise. > (mve_vqdmulltq_m_s<mode>): Likewise. > (mve_vqrshrunbq_m_n_s<mode>): Likewise. > (mve_vqrshruntq_m_n_s<mode>): Likewise. > (mve_vqshrunbq_m_n_s<mode>): Likewise. > (mve_vqshruntq_m_n_s<mode>): Likewise. > (mve_vrmlaldavhaq_p_uv4si): Likewise. > (mve_vrmlaldavhaxq_p_sv4si): Likewise. > (mve_vrmlsldavhaq_p_sv4si): Likewise. > (mve_vrmlsldavhaxq_p_sv4si): Likewise. > > gcc/testsuite/ChangeLog: > > 2019-10-31 Andre Vieira <andre.simoesdiasvie...@arm.com> > Mihail Ionescu <mihail.ione...@arm.com> > Srinath Parvathaneni <srinath.parvathan...@arm.com> > > * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.
